公开(公告)号：JP2004214628A

公开(公告)日：2004-07-29

申请号：JP2003396341

申请日：2003-11-26

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： HIIMYONGU PAAKU ,  LEE BYOUNG H ,  PAUL D AGUNERO ,  SCHEPIS DOMINIC J ,  SHAHIDI GHAVAM G

IPC: H01L21/28 ,  H01L21/00 ,  H01L21/336 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/01 ,  H01L27/08 ,  H01L27/092 ,  H01L27/12 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/74 ,  H01L29/76 ,  H01L29/78 ,  H01L29/786 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L29/78612 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/41783 ,  H01L29/66772

Abstract: PROBLEM TO BE SOLVED: To provide the structure of a CMOS device and a method for manufacturing the CMOS device.
SOLUTION: The manufacturing method comprises a process of sticking an SOI wafer 20 having prescribed thickness to the surface of a buried oxide (BOX) substrate 10, a process of forming a gate dielectric 25 on the surface of the SOI wafer 20, a process of forming a shallow trench isolation (STI) area 35 so as to form an almost round corner on the BOX substrate 10, a process of forming gate structure on the surface of the gate dielectric 25, a process of sticking a driving layer to the surface of the SOI wafer 20, a process for executing either one of N-type dopant implanting and P-type dopant implanting in the SOI wafer 20 and the implanting layer, and a process of forming a source/drain region 79(a) from the implanting layer and the SOI wafer 20. The source/drain region 79(a) has thickness larger than the prescribed thickness of the SOI wafer 20, and the gate dielectric is arranged lower than the STI region 35.
COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：JP2000200832A

公开(公告)日：2000-07-18

申请号：JP36394999

申请日：1999-12-22

Applicant: IBM

Inventor： PAUL D AGUNERO ,  REENA P BUCKWALTER ,  JOHN HAMEL ,  BARBARA LUTHER ,  STAMPER ANTHONY K

IPC: H01L23/522 ,  H01L21/04 ,  H01L21/28 ,  H01L21/318 ,  H01L21/768

Abstract: PROBLEM TO BE SOLVED: To improve adhesiveness of a deposited inorganic barrier film to a copper surface of a copper interconnection structure by including exposure of a copper layer in an interconnected semiconductor structure to a reducing plasma before the formation of the inorganic barrier film on the copper interconnection structure. SOLUTION: A copper interconnection structure is exposed to a reducing plasma before an inorganic barrier film 24 is deposited. This reducing plasma is a non-oxidizing, i.e., oxygen-atom-free plasma atmosphere. A suitable plasma is selected from H2, N2, NH3, and rare gas, but it is not limited to these. Further, a combination of more than two of these reducing plasmas such as N2 and H2 is intended. N2 and NH3 are very preferable among these reducing plasmas. The adhesiveness of the inorganic barrier layer 24 to copper 20 can be improved by using this reducing plasma exposure process.