公开(公告)号：US3609744A

公开(公告)日：1971-09-28

申请号：US3609744D

申请日：1968-03-15

Applicant: IBM

Inventor： PEARSON KENNETH A

IPC: G09G1/12 ,  H01J29/70

CPC classification number: G09G1/12

Abstract: A device for generating a character upon a CRT tube consisting of a pulse generator placing a pulse upon a delay line which is capacitively coupled to three etched sense wires, the voltages induced on said wires ultimately controlling the X-deflection, the Y-deflection, and the unblanking function of the CRT tube. Before the voltages are applied to the CRT tube, the correct sense wires are selected and the voltages thereon are amplified.

公开(公告)号：US3473078A

公开(公告)日：1969-10-14

申请号：US3473078D

申请日：1967-01-12

Applicant: IBM

Inventor： LAZARCHICK NICHOLAS JR ,  PEARSON KENNETH A

IPC: G09G1/10 ,  G09G1/12 ,  H03K17/60 ,  H03K17/64 ,  H01J29/70

CPC classification number: G09G1/10 ,  G09G1/12 ,  H03K17/60 ,  H03K17/64

公开(公告)号：CA1204852A

公开(公告)日：1986-05-20

申请号：CA437405

申请日：1983-09-23

Applicant: IBM

Inventor： PEARSON KENNETH A ,  ZIMMERMAN LUTHER L

IPC: H04N1/387 ,  G06T3/40 ,  H04N1/40 ,  H04N1/00

Abstract: Apparatus and method for converting image data of an image matrix to an image matrix having a different number of matrix points. Each new image pel has a gray scale determined by considering its position with respect to the nearest neighbors of an original image pel. A look up table is provided having a plurality of planes, each plane including a plurality of storage elements arranged in columns and rows. The storage elements contain the gray scale level of a new image pel. The look up table plane represents the gray scale levels for a plurality of positions within the neighborhood. The planes are addressed by the gray scale levels of the pels comprising the neighborhood, and the storage elements within a plane are addressed by the position of the new pel with respect to the neighbors.

公开(公告)号：CA1252576A

公开(公告)日：1989-04-11

申请号：CA500423

申请日：1986-01-27

Applicant: IBM

Inventor： PEARSON KENNETH A ,  ZUCKER LARRY R

IPC: H03K19/177 ,  G06F7/00 ,  G06F17/50 ,  H03K19/173

Abstract: A programmable, sequential logic array for performing logical operations within a memory array, including an input storage array having addressable locations for storing input control words, input means for receiving a plurality of input signals and control words from the input storage array and producing signals indicating the relationship between conditions of the input signals and conditions represented by the control words, output means for providing binary output signals, an output storage array having addressable locations for storing output control words for con trolling a state of the output means, a next address storage array for identifying a next address from one of a plurality of fields within the next address array, address generation means for receiving address signals from the next address storage array and for applying the address signals to address circuits of the input storage array, the output storage array, and the next address storage array, coding means for coding status of lines comprising an input/output interface for selectively ignoring predetermined status conditions, control means connecting the input means to the output means and responsive to signals produced by the input means to enable the output means to respond to selected output control words to selectively change outputs, and a subroutine control random access storage array for providing signals to the control means to control execution of subroutines.

公开(公告)号：CA876950A

公开(公告)日：1971-07-27

申请号：CA876950D

Applicant: IBM

Inventor： PEARSON KENNETH A