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    ADDRESS CONVERSION PROCESSING METHOD
    1.
    发明专利
    ADDRESS CONVERSION PROCESSING METHOD 失效

    公开(公告)号：JPS60171552A

    公开(公告)日：1985-09-05

    申请号：JP23870084

    申请日：1984-11-14

    Applicant: IBM

    Inventor： PIITAA HAAMAN GAMU ,  ROJIYAA ERUDORETSUDO HOFU ,  PIITAA HAAMANSU TOORUMAN ,  TOOMASU OSUKAA KAARII SAADO

    IPC: G06F9/455 ,  G06F9/48 ,  G06F12/10

    Abstract: The disclosed embodiments enable address translations for a virtual machine in the TLB (translation lookaside buffer) of a CPU to be retained from exiting a SIE (start interpretive execution) instruction to the next SIE entry to interpretive execution for the same guest (virtual machine CPU). Conditions are defined which determine when guest TLB entries must be invalidated. These conditions require invalidation of guest TLB entries only within and on entry to interpretive execution. A single invalidation (34) of guest TLB entries on entry (30) to interpretive execution is required for any number of conditions recognized while a CPU is not in interpretive execution state. For a guest virtual multi-processor (MP) machine, an interlock is provided to allow the use of guest virtual addresses by host instruction simulation and the need for guest TLB invalidation is broadcast to all other real CPUs in a real MP system so that all guest TLBs on all real CPUs can be invalidated to maintain integrity. No broadcast or interlock is needed for a guest virtual uni-processor (UP) machine.

    METHOD OF RECOGNIZING I/O INTERRUPTION SUBCLASS
    3.
    发明专利
    METHOD OF RECOGNIZING I/O INTERRUPTION SUBCLASS 失效

    公开(公告)号：JPH05204679A

    公开(公告)日：1993-08-13

    申请号：JP18511192

    申请日：1992-07-13

    Applicant: IBM

    Inventor： NOOMAN CHIYOOCHIYUN CHIYOU ,  PIITAA HAAMAN GAMU ,  ROOJIYAA ERUDORETSUDO HIYUU ,  MUUN JIYU KIMU ,  JIEIMUSU CHIESUTAA MAZUROOSUKI ,  DONARUDO UIRIAMU MATSUKOORII ,  KIYASUPAA ANSONII SUKARUZUI ,  JIYON FUENTON SUKANRON ,  RESURII UTSUDO WAIMAN

    IPC: G06F9/46 ,  G06F9/48

    Abstract: PURPOSE: To provide a system in which the number of customer sections can exceed the number of I/O interruption subclasses constituted in the system. CONSTITUTION: This is a logically sectioned data processing system and mutually different sections possibly include operating systems of different customers. A CPU interface performs control for making plural CPUs respond to I/O interruptions arranged in many hardware control queues. A host hypervisor program nominates a customer operating system and the customer uses an I/O interruption when controlling the nomination of a program on a CPU. The number of the sections of the customers can exceed the number of I/O interruption subclasses constituted in the system and the nomination control of the operating systems of the customers can be adapted to different priority of plural programs operating under the respective customers. Then CPU control which can support a warning to the host as to a possible I/O interruption can be performed and a CPU which enables the I/O of a customer is provided with a controlled pass-through.

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