公开(公告)号：CA1250665A

公开(公告)日：1989-02-28

申请号：CA506148

申请日：1986-04-09

Applicant: IBM

Inventor： PICON JOAQUIN ,  POIRAUD CLEMENT Y G ,  SAZBON-NATANSOHN DANIEL

IPC: G11C29/04 ,  G06F9/06 ,  G06F9/26 ,  G06F9/445 ,  G06F12/06 ,  G06F11/00

Abstract: A method and associated addressing circuit for storing the control code of a processor in a read only memory (ROM) and in a read/write memory RAM comprising a code area and a patch area. It consists in virtually dividing the control code in blocks of n instructions, storing the first instruction of each block into the code area of the read/write memory, and storing the n-1 following instructions of each block in the read only memory ROM. When an error is detected in at least one block, the first instruction of said block normally stored in the read/write RAM, is replaced by a branch instruction containing a branch address value so as to point to the patch area where the corrected block is stored.