公开(公告)号：DE2422956A1

公开(公告)日：1975-01-16

申请号：DE2422956

申请日：1974-05-11

Applicant: IBM

Inventor： COWARDIN ROBERT LEWIS ,  MATUCK GEORGE COLEMAN ,  MCCRAY CHARLES MARTIN ,  POWELL FLAVIUS MORTON ,  PRATT WOODROW WILSON ,  THOMAS DELBERT CLAYTON ,  THORNE WILLIAM DUNCAN

IPC: B41J2/24 ,  B41J3/00 ,  B41J11/04 ,  B41J11/48 ,  B41J19/16 ,  B41J25/304 ,  G06K15/02 ,  H04N1/29 ,  B41J3/02 ,  G06K15/10

Abstract: A printer is disclosed in which a character forming print head is disposed on a carriage which pivots about a central point to describe an arcuate path, adjacent to which is situated an arcuate platen. The media to be marked upon conforms to the arcuate shape of the platen. The print head oscillates or reciprocates from one end of the arc to the other, and back. The arcuate path length may be varied to encompass printing in one or more coplanar stations on an arc in the plane of the print head and pivot.

公开(公告)号：DE1201586B

公开(公告)日：1965-09-23

申请号：DEI0015305

申请日：1958-08-27

Applicant: IBM DEUTSCHLAND

Inventor： RENT EDWARD FRANCIS ,  POWELL FLAVIUS MORTON

IPC: G06F9/48

Abstract: 893,555. Digital electric calculating apparatus. INTERNATIONAL BUSINESS MACHINES CORPORATION. Sept. 4, 1958 [Sept. 6, 1957], No. 28431/58. Class 106 (1). A data processing machine of the stored programme type comprises input and output means, means for performing a main sequence of operations in accordance with programme words successively presented by an address control device, programme interrupt means operable in response to a signal from the input or output means to interrupt the main sequence of operations and to condition the address control device to cause performance of a further sequence or plurality of sequences of operations independent of the main sequence, and interrupt storage control means effective at the end of the independent sequence or sequences of operations for automatically returning the machine to the point in the'main sequence of operations where the interruption occurred. The electronic computer described is generally similar to that described in Specification 800,273. 10-decimal-digit words are stored serially in the main magnetic drum store GS, each digit being represented in parallel by a two-out-of-five bit code. Each instruction comprises a 2-digit operation or function part which is set up in register OPR (together with a checking sign), and two addresses which are set up in register PR. A normal programme step comprises two parts: (1) an " I " or " Instruction " part, in which the right-hand address in PR (address of the next instruction) is transferred to address register AR and controls selection circuits AS for reading out the next instruction from GS to OPR and PR; (2) a " D " or " Data " part, in which the left-hand address in PR is transferred to AR and is also entered together with the operation digits in operation matrix OM which controls the performance of the instruction. In the present computer each instruction address set up in AR is copied into an interrupt register IR which thus indicates the point of return to the normal programme sequence should an " interrupt " signal be received. Such a signal may come from drum buffer storage A (associated with punched card input 11, 12) or B (associated with an output punch-not shown), or from a magnetic tape unit TU1, TU2. Each tape unit comprises six tapes and is coupled to a core storage unit CS via a timing ring TR1 or TR2. The units TU1, TU2 operate independently whereby e.g. data may be simultaneously written into one unit and read from the other. The " data address " part of a tape instruction determines which tape is selected the operation (e.g. read, write or rewind) and whether a tape control " interrupt " operation shall occur. The interrupt operations mainly relate to checking input/output devices (details of the check not specified). Reference is made to manual selection by a switch of the devices to be operated on an interrupt basis. Interrupt operations.-An " interrupt " signal may be obtained, e.g. when a card has been read into buffer storage A or when the end of a record is detected on one of the tapes. This signal triggers an associated " latching" circuit in control circuits (Figs. 5a and 5b, not shown) which also include error-detecting and delay circuits. If no error is detected, the latching circuits supply a signal to cause a predetermined address (corresponding to the buffer storage or tape unit which caused the interrupt operation) to be transferred from control console 15 to address register AR. This address gives the first instruction of the interrupt routine, the programme sequence being performed in the same manner as for the normal programme except that the input circuit 22 to the interrupt register is blocked. The interrupt routine ends with a " release " instruction whose " data " address releases the operated interrupt control circuits and whose " instruction " address selects the interrupt register IR; the contents of IR are then transferred to register PR to effect a return to the normal programme. This return is delayed if, in the meantime, other interrupt signals have been received, the interrupt operations being effected in turn according to a predetermined order of priority. For tape. controlled interrupt operations, the first instruction is taken from a predetermined address in the core storage unit CS. Circuit details.-The circuits consist primarily of diode gates and triode cathode followers and inverters. The registers PR and SR comprise shift registers of the type in which each stage comprises a "latch ring " circuit. Specifications 782,373, 803,003 and U.S.A. Specification 2,959,351 also are referred to.