公开(公告)号：JPH11175459A

公开(公告)日：1999-07-02

申请号：JP9333698

申请日：1998-04-06

Applicant: IBM

Inventor： JERRY DON LEWIS ,  JOHN STEPHEN DODDSON ,  RAVI KUMER ARMIRI

IPC: G06F12/08 ,  G06F13/18 ,  G06F13/42 ,  G06F15/16 ,  G06F15/173

Abstract: PROBLEM TO BE SOLVED: To perform fast transfer of a bus operation that is strictly ordered by deciding whether or not at least one processor receives the 1st response to the 1st bus operation. SOLUTION: Plural bus operation, e.g. storage elements are issued from processors 102a to 102c. When the 1st response which shown that one of the bus operations should be issued again is received by the processor 102a to 102c and when it shows that one of issued bus operations is issued again, 2nd response which shows that at least another of the issued bus operations is issued again is issued from the processors 102a to 102c. The 2nd response is called self-retrial response. The processor 102a to 102c provide self-retrial response to all of bus operation requests that are issued after bus operation requests which are issued after a bus operation request that receives the first retrial response.