公开(公告)号：JPH06282528A

公开(公告)日：1994-10-07

申请号：JP31961993

申请日：1993-12-20

Applicant: IBM

Inventor： ALLEN MICHAEL S ,  MOORE CHARLES R ,  REESE ROBERT J

IPC: G06F15/16 ,  G06F12/08 ,  G06F15/177

Abstract: PURPOSE: To provide a method and system for improving the efficiency of data transfer of a data processing system. CONSTITUTION: Each of many processors 10 has an attached buffer for storing data transferred through a common bus 8. The common bus 8 connects the processors and memories to each other. Each processor 10 continuously monitors the common bus during a specific period after another processor tries to perform operation and can send a selected control signal when the tried operation nearly contravenes data coherence in the data processing system. When the control signal is sent onto the common bus, data transfer from the buffer to the processor is inhibited. When the control signal is not sent out onto the common bus, the data transfer from the buffer to the processor is allowed.

公开(公告)号：CA2109043A1

公开(公告)日：1994-07-30

申请号：CA2109043

申请日：1993-10-22

Applicant: IBM

Inventor： MOORE CHARLES R ,  MUHICH JOHN S ,  REESE ROBERT J

IPC: G06F13/16 ,  G06F12/08 ,  G06F13/36 ,  G06F13/38 ,  G06F13/40 ,  H04L12/40

Abstract: SYSTEM AND METHOD FOR TRANSFERRING INFORMATION BETWEEN MULTIPLE BUSES A method and system are provided for transferring information between multiple buses. Information is transferred through a first bus between multiple first bus devices. Information is transferred through a second bus between multiple second bus devices. Information is transferred through logic means between the first and second buses. Using the logic means, an action of a first bus device is enabled in response to a condition in which a second bus device waits for the action while the first bus device waits for a separate action on the second bus.

公开(公告)号：CA2260312A1

公开(公告)日：1999-08-19

申请号：CA2260312

申请日：1999-01-25

Applicant: IBM

Inventor： REESE ROBERT J ,  LENK PETER S ,  MAYFIELD MICHAEL J ,  VADEN MICHAEL T

IPC: G06F15/177 ,  G06F9/46 ,  G06F9/52 ,  G06F15/16

Abstract: In a multiprocessor system, when a store request has stalled, a signal is generated and sent to all processors indicating such a stalled store situation. In response, all processors will postpone the sending of load, or read, requests to memory until the stalled store request has completed.

公开(公告)号：CA2113867A1

公开(公告)日：1994-07-21

申请号：CA2113867

申请日：1994-01-20

Applicant: IBM ,  MOTOROLA INC

Inventor： ALLEN MICHAEL S ,  MOORE CHARLES R ,  REESE ROBERT J

IPC: G06F15/16 ,  G06F12/08 ,  G06F15/177

Abstract: A method and system for the enhanced efficiency of data transfers from memory to multiple processors in a data processing system. Each of the multiple processors has an associated buffer for storing data transferred via a common bus which couples the processors and memory together. Each of the multiple processors continually monitors the common bus and is capable of asserting a selected control signal in response to an attempted activity of another one of the multiple processors which would violate data coherency within the data processing system during a particular period of time following the attempted activity. Data is transferred from memory to a buffer associated with one of the multiple processors and stored in the buffer in response to a request from the processor associated with the buffer prior to expiration of the particular period of time and prior to a determination of whether or not this transfer will result in a possible data coherency problem. The common bus is continually monitored during the particular period of time. Transfer of the data from the buffer to the processor is prohibited in response to a presence on the common bus of the selected control signal prior to expiration of the particular of time. Transfer of the data from the buffer to the processor is permitted in response to an absence on the common bus of the selected control signal.