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    1.
    发明专利
    未知

    公开(公告)号：DE1187404B

    公开(公告)日：1965-02-18

    申请号：DEJ0022002

    申请日：1962-06-26

    Applicant: IBM

    Inventor： FLEISHER HAROLD ,  ROTH ROBERT INGERSOLL

    IPC: G11C15/06

    Abstract: 981,919. Digital data storage; electric calculating apparatus. INTERNATIONAL BUSINESS MACHINES CORPORATION. June 26, 1962 [June 26, 1961], No. 24451/62. Headings G4A, G4B and G4C. Words can be selected in a memory according to specified characteristics and a selected field of each word added together the sum appearing in a register without the words being removed from the memory. Embodiments described use cryotrons or relays. In the cryotron store of Fig. 4 words are stored in rows of bi-stable circuits 10a to 10c, 12a to 12c . . ., like ordered binary digits forming the columns of the matrix. The state of a circuit and the value of the digit stored therein is represented by current flowing in one limb or the other of a superconductive loop. A mask register is set to determine the field of the words on which a selection is made. An association selection register is set to determine the value of the field on which a selection is made and the sum field selection register is set to determine the field of the selected words to be summed by the counting networks, the result appearing in register 124. The counting networks are as described in Specification 923,770. Indicators 97 to 100 such as lamps are operated when a word is selected. A network 102 counts the number of such words, operating in the same way as networks 120, and places the results in register 106. A detail of Fig. 4 is shown in Fig. 5G. The mask register 108 element 110a if set to 0 cuts off current to the like order association selection register 84 element 86a. If the order shown in Fig. 5G is to be masked current is steered by means not shown into the right-hand conductor of the pair 226a and switch 228 is closed. Gates 242a, 148a, 154a and 156a become resistive and no current appears on conductor 146a which supplies the select register. Assuming mask register set to 1 a similar process involving switch 230 determines whether current in conductor 146a is steered to conductors 46 or 48, representing 0 or 1 respectively. The bit represented by the setting of circuit 86a is compared with the bits stored in the bistable devices 10a, 12a &c. If device 10a for example stores a bit different from the setting of circuit 86a current from a source not shown is steered to line 66 since either gates 10 and 62 or 58 and 64 are resistive. If the bit values are the same either line 50 or 52 carries current depending on the setting of device 10a. To select a word order for inclusion in the field to be summed current is steered to the left hand line of the pair 226a. This leads to the marking of the select line. If the suppress line had been marked gate 172 would be resistive and device 10a would be seen by the counting network as if it were storing 0. Similarly if the word in the first row is not chosen current in line 66 closes gates in the counting network which make it appear that device 10a is storing 0. Fig. 7 shows a multiplier which has as operands two fields of the sum register. If the value of multiplier bit is 1 the values of the multiplicand are gated from circuits 408c to counting networks according to the order of the multiplier bit. A dividing circuit is also mentioned in which the dividend is the contents of the sum register and the divisor the number of selected words taken from the register 126. It is stated to be of conventional construction and no further details are given. A relay circuit is shown in Fig. 8A. To enter a 1 into storage device 440b word write line 463 is energized and switch 462b closed. This energizes both the P coils of solenoid 448b and their combined strength is sufficient to switch the contacts which inter alia cause a hold coil of the solenoid to be energized and by-pass the coils to 0 solenoid 444b. The value in circuit 440b is the same as that in the association select register, as indicated by energization of solenoid 468b or 470b, either contacts 472b and 482b or contacts 476b and 484b will be closed, and current on line 488 will energize solenoid 492. A counting network is also provided in this embodiment and the first level comprises contacts 502b, 504b.

    2.
    发明专利
    未知

    公开(公告)号：DE2318445A1

    公开(公告)日：1973-12-13

    申请号：DE2318445

    申请日：1973-04-12

    Applicant: IBM

    Inventor： ROTH ROBERT INGERSOLL

    IPC: G11C19/00 ,  H04L9/00 ,  H04L9/34

    Abstract: Information is shifted from any one or a number of stages in a shift register to any other one or other stages of a shift register by use of gating circuits connected to each stage operated by a control circuit. The gating circuits connected to each stage of the register are operative to either inhibit storage of input information therein and transfer of stored information by stage disconnect while allowing immediate passage of such information to the next succeeding stage by immediate transfer connect, or to allow storage of input information therein and transfer of stored information by stage connect while inhibiting immediate passage of such information to the next succeeding stage by immediate transfer disconnect.

    4.
    发明专利
    未知

    公开(公告)号：DE1058101B

    公开(公告)日：1959-05-27

    申请号：DEI0009554

    申请日：1954-12-22

    Applicant: IBM DEUTSCHLAND

    Inventor： ROTH ROBERT INGERSOLL ,  JOHNSON REYNOLD BENJAMIN

    IPC: H01C8/02

    Abstract: 758,508. Electric digital-data-storage apparatus. INTERNATIONAL BUSINESS MACHINES CORPORATION. Dec. 21, 1954 [Dec. 24, 1953], No. 36898/54. Class 106 (1). A data storage device utilizes the physical phenomenon that if two electrodes are placed in a mixture of finely divided metallic particles and a non-conducting fluid, and if a high potential is momentarily applied across the two electrodes, then the metallic particles are drawn towards the electrodes and form a conductive path between them which path remains, even when the potential is removed, until the mixture is agitated to redisperse the metallic particles. In the particular embodiment described a number of metal containers hold the mixture (tricresyl phosphate and iron filings) each one 17, Figs. 1 and 2, being supported on a bridge plate 19 insulated from a base plate, and each one having associated with it a set of 10 electrodes 42 which extend into the mixture and which are supported on a frame 39 pivoted at either end by links 35, 36 to a second frame 28 slidably mounted on pins 26 to be able to move in a direction parallel to the base plate. A spring 47 tends to move the upper frame 39 to the right, Fig. 2, but this is prevented by a member 49a, and a spring 44 tends to keep the lower frame 28 in contact with a fixed abutment 46. In operation data is entered by first energizing a solenoid to lift the member 49a, thus releasing the upper frame and allowing it to move to the right and downwards, bringing each electrode to a distance of 0.025 inch from the base of its associated container, and data is entered into a particular container by applying a high-potential pulse (300 V.) between the container and a selected electrode thus forming a conductive path between the selected electrode and the base of the particular container. A 10- key keyboard controlled circuit is described for entering data successively into each container. Data stored in a particular container is read out by applying a voltage to the particular container and observing to which of the associated 10 electrodes the voltage is transmitted. An electrical read-out circuit suitable for controlling a record-card punch is described. The store is cleared by momentarily energizing a solenoid 60 which causes the lower frame 28 to be pulled to the left, Fig. 2, and by de-energizing the first mentioned solenoid so that as the lower frame moves to the left, back to its original position under control of the spring 44, the link 35 engages the member 49a and raises the electrodes returning them to their original positions, thus the device is reset and each container of fluid is agitated.

    6.
    发明专利
    未知

    公开(公告)号：DE941938C

    公开(公告)日：1956-04-19

    申请号：DEI0002962

    申请日：1950-10-01

    Applicant: IBM DEUTSCHLAND

    Inventor： ROTH ROBERT INGERSOLL

    Abstract: 698,674. Supply systems for discharge lamps. BRITISH TABULATING MACHINE CO., Ltd. April 17, 1950 [April 19, 1949], No. 9375/50. Drawings to Specification. Class 38 (iv). [Also in Groups XIX, XX and XL (b)] In a machine for making photographic film records of punched record cards, a fluorescent discharge lamp for exposing through cardcontrolled shutters a continuously moving photographic film is fed from a multivibrator so that the discharge frequency is sufficiently raised to avoid striations appearing across the width of the exposed and developed film record, which comprises a dark ground having clear spots in positions corresponding to the card perforations.

    7.
    发明专利
    未知

    公开(公告)号：DE1174541B

    公开(公告)日：1964-07-23

    申请号：DEJ0022561

    申请日：1962-10-27

    Applicant: IBM

    Inventor： ROTH ROBERT INGERSOLL ,  FLEISHER HAROLD

    IPC: G06E1/04 ,  G06F7/38 ,  G11C11/44 ,  H03M7/12

    Abstract: 978, 659. Digital electric calculating. INTERNATIONAL BUSINESS MACHINES CORPORATION. Oct. 29, 1962 [Oct. 30,1961], No. 40721/62. Heading G4A. A plurality of multidigit binary coded decimal numbers are added simultaneously using current steering techniques. The circuits particularly described use cryotron gates and cryotron adding trees as disclosed in Specification 923,770 which sum n binary digits by marking 1 out of n + 1 output lines and recode this output into binary form. The decimal numbers N1 to N36 (Fig. 1) provide inputs to sets of adding trees 102 to 105. Each decimal digit is in the 1-2-4-8 code and, for example, all the "1" order bits in the units order digits are summed in the trees 111, 121, 131, and 141. Tree 111 sums the bits in numbers N1 to N9 and marks one out of ten outputs; tree 121 receives this output and also signals representing the "1" order bits in the units order digit of numbers N10 to N18, marking one out of ten output lines and possibly a carry line to adding tree 125 which operates on "1" order bits in the tens order of the decimal numbers, i.e. each bit has a decimal weight of ten. Adding trees 131,141 are identical with tree 121. Each D decoder now sums the weighted values of the marked outputs from its corresponding adding tree and generates carries. The D decoder 152 for the tens decimal order is shown in Figs. 5a to 5c. Decoder 152 converts the one out of ten markings into a 1-2-4-6-8 representation of their digital sum and produces carries into an E decoder of the next higher order (not shown). Suppose that the sum of the "1" bits in the tens order is 7; of the "2"bits: 4; of the "4" bits; 3; and of the "8" bits: 5. The output of circuit 145 (Fig. 5) then represents 7 tens and is registered in decoder 152 as 00111; the output of circuit 146 represents 8 tens and is registered in decoder 152 as 10000; the output of circuit 147 represents 12 tens and is registered as 00010 with a carry of one hundred; the output of circuit 148 represents 40 tens and is registered as 00000 with a carry of four hundred. The five bit numbers are added by counting to give a sum 10121 represented by marking terminals 554S1,555S0,553S1,552S2 and 551S1. The carries are represented by marking terminals 541C, 542D, 543C, 544C, 545C and 546D. As an example consider the output from circuit 145. Line 421S7 has current flowing in it and sends cryotron gates resistive to stear current into the right limbs of loops 501, 502 and 506 and the left limbs of loops 510, 514. This in turn steers current into the lower limbs of loops 534, 525 and 529 and the upper limbs of loops 533, 537, which steers current into the left branches of adding trees starting at terminals 551, 552 and 553 and the right branches of trees starting at terminals 554, 555. E decoder 162 for the tens order is shown in Figs. 6a to 6c. Its inputs are the 1-2-4-6-8 coded sum from the D decoder 152, the carries from the previous order D decoder 151, and the carries from the previous order E decoder 161. Adding tree 601 sums the "1" bits and has as inputs the "1" bit sum from the D decoder, three "1" bit carries from the previous order D decoder (corresponding to the "one hundred" carries in Fig. 5c) and three "1" bit carries from the previous E decoder. One out of the eight lines 601S0 to 601S7 is marked and in circuit 605 this marking is decoded into a three bit binary number of which the highest order bit is an input to the "4" bit adding tree 603, the next order bit is an input to the"2" bit adding tree and the lowest order bit is the final sum "1" bit of the tens decimal order and is registered by the state of the current in the loop FS1. Adding trees 602 to 604 sum the "2", "4" and "8" bits to mark one out of a set of outputs. Decoders 606 to 608 code this marking into some or all of the following: (a) Markings representing digital values 20, 40 or 80; (b) Markings representing carries of 100 to 200 into the next order E decoder; and (c) Markings representing digital values 60 or 120. The markings (a) and (c) are, together with the "6" bit sum from the D decoder, inputs to an asymmetrical adding tree 609 of which the output is marking on one out of thirty-eight lines. Finally, decoder 610 translates this marking into "2", "4" and "8" bits and carries of one and or two hundred. An application of the adder to binary to coded decimal conversion is described in which coded values of 2‹ to 2 35 are stored in the registers N1 to N36 and only the relevant registers are summed, those registers whose orders in the number being converted contain zeroes being treated as empty (Fig. 7, not shown). Specification 862,178 also is referred to.

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