公开(公告)号：DE3380710D1

公开(公告)日：1989-11-16

申请号：DE3380710

申请日：1983-02-23

Applicant: IBM

Inventor： LAVALLEE RUSSELL WILLIAM ,  RYAN MEADE PHILIP ,  SOLLITTO VINCENT FRANCIS

IPC: G06F12/16 ,  G11C29/00 ,  G06F11/20

Abstract: A single error correcting memory is constructed from partially good components on the design assumption that the components are all good. Those small number of logical lines containing double-bit errors are replaced, when detected, by good lines selected from a replacement area of the memory. The replacement area is provided by a flexibly dynamically deallocated portion of the main memory so that it can be selected from any section of the original memory by inserting the appropriate page address in the replacement page register. With such a memory architecture, until the first double-bit error is detected (either in testing or actual use), all pages may be used for normal data storage. When such an error is detected, some temporarily unused page in the memory is deallocated, that is rendered unavailable for normal storage, and dedicated to providing substitute lines. The same procedure is followed for subsequent faults. If the replacement area itself becomes defective, a different page may be chosen to provide substitute lines simply be providing a different address in the replacement page register.