公开(公告)号：CA1227585A

公开(公告)日：1987-09-29

申请号：CA457027

申请日：1984-06-20

Applicant: IBM

Inventor： KUMMER DAVID A ,  SAENZ JESUS A ,  TRYNOSKY STEPHEN W

IPC: G09G5/00 ,  G06F3/00 ,  G06F3/14 ,  G06F7/02 ,  G06T7/00 ,  G09G1/16 ,  G09G5/02 ,  G09G5/393 ,  G09G5/395 ,  G09G1/00

Abstract: RASTER SCAN DIGITAL DISPLAY SYSTEM WITH DIGITAL COMPARATOR MEANS In a bit mapped raster scan digital display system, a number of maps each contain a single component of the display data and are read together to provide sets of bytes, each set representing eight pel defining groups. A compare system is provided for determining when a pel group in a set of bytes compares with a reference pel defining group. For the, or each, pair of maps, the compare system compares all bits of the two bytes of data with the associated bit of the reference group to provide outputs when a corresponding bit in each of the bytes compares with the two reference bits. When more than two maps are employed the compare outputs related to all of the pairs of maps are combined to provide an output signal when a pel group in a byte from the maps compares with the reference bits. In a modification of the system the comparison can be made between one or more of the maps and the corresponding bit or bits of the compare data.

公开(公告)号：CA1220293A

公开(公告)日：1987-04-07

申请号：CA458370

申请日：1984-07-06

Applicant: IBM

Inventor： KUMMER DAVID A ,  SAENZ JESUS A ,  TRYNOSKY STEPHEN W

IPC: G09G5/00 ,  G09G5/34 ,  G09G5/395 ,  G09G1/16

Abstract: RASTER SCAN DIGITAL DISPLAY SYSTEM In a raster scan digital display system, a display image is stored, as coded characters or a bit map, which is larger than the display image. In order to define an image, within the stored image, for display, the addressing system for the memory (or memories) storing the image include a display image defining circuit. This circuit includes an address counter which is incremented to define successive addresses of data in a line of the displayed image, or row of characters therein. The circuit includes a first register to receive the initial address of a display image and a second register to receive a value indicating the width of the stored image. For the initial line (or character row) of a displayed image, the address counter is loaded from the first register and incremented from the initial address. For each subsequent line (or character row) the address from which the counter is incremented is the sum of the initial address of the previous line (or character row) and the value in the second register.

公开(公告)号：GB2104757A

公开(公告)日：1983-03-09

申请号：GB8222695

申请日：1982-08-06

Applicant: IBM

Inventor： EGGEBRECHT LEWIS C ,  SAENZ JESUS A

IPC: G06F1/24 ,  G06F3/00 ,  G06F3/02 ,  G06F13/00 ,  H04L25/38 ,  H04L23/00

Abstract: A serial keyboard interface (28) connects a self scanning programmable serialized keyboard (40) to the system bus (10) of a data processing system. A cable (42) containing only a clock wire (52) and a data wire (58) provides the connection. The keyboard transmits a 9-bit scan out code consisting of a start bit followed by eight serial data bits. The keyboard clock line (52) is connected to the clock or shift terminal of a serial-to-parallel shift register encoder (62) for shifting the data bits on data line (58) into the encoder which has eight parallel output data lines (A, B . . . G, H) connected to the system bus. When the encoder (62) contains a complete scan out frame, the start bit is in the most significant stage (h') and sets the D-type latch (68) to apply a CPU interrupt request to the system bus (10). At this time, the &upbar& Q output of latch (68) pulls down the data line to ground potential, thereby disabling the data line and preventing further keyboard transmission of data. When the interrupt request is granted by the CPU, a clear signal resets latch (68) to remove ground potential from data line (58) and thereby permit further transmission of data.

公开(公告)号：CA1235537A

公开(公告)日：1988-04-19

申请号：CA481698

申请日：1985-05-16

Applicant: IBM

Inventor： RACKLEY DARWIN P ,  SAENZ JESUS A ,  YOSIM PAUL S

IPC: G09G5/18 ,  G06F3/153 ,  G09G1/16 ,  G09G1/28 ,  G09G5/00 ,  G09G5/02 ,  G09G5/04 ,  G09G5/36

Abstract: DIGITAL DISPLAY SYSTEM A digital display system includes a monitor arranged to receive digital display data and synchronizing signals to develop displays on a cathode ray tube. The monitor is switched between different line structure and/or color definition modes in response to the polarity of one of the vertical or horizontal synchronizing signals trains. A circuit receives this train to provide control signals to the horizontal time base and/or a color signal code converter. The time base control signal, in accordance with its binary value, controls the frequency of the time base. The color converter, in response to the control signals, either passes color signals received in parallel over six input lines without change to the cathode ray tube drive circuits or converts color signals on four of the input lines to output signals on the six lines to the drive circuits.

公开(公告)号：CA1172386A

公开(公告)日：1984-08-07

申请号：CA403583

申请日：1982-05-21

Applicant: IBM

Inventor： EGGEBRECHT LEWIS C ,  KUMMER DAVID A ,  SAENZ JESUS A

IPC: G06F3/153 ,  G09G5/12 ,  G09G5/18 ,  G09G1/16

Abstract: SYNCHRONIZATION OF CRT CONTROLLER CHIPS Two controller units controlling a single input/ output device such as a cathode ray tube (CRT) are synchronized by a command signal. Upon appearance of the command signal, the slave controller unit, which may have been running unsynchronized with the master controller, is stopped at the time for vertical retrace and remains stopped until vertical retrace time for the master controller. At this point, the slave controller is restarted in synchronism with the master controller and remains synchronized so long as both master and slave receive the same clock and the same screen refresh parameters.

公开(公告)号：CA1224291A

公开(公告)日：1987-07-14

申请号：CA457026

申请日：1984-06-20

Applicant: IBM

Inventor： KUMMER DAVID A ,  RACKLEY DARWIN P ,  SAENZ JESUS A

IPC: G09G1/06 ,  G09G1/16 ,  G09G5/00 ,  G09G5/40 ,  G09G1/00

Abstract: RASTER SCAN DISPLAY SYSTEM A raster scan display system includes a plurality of storage maps. These maps are addressable in either of two modes. In the first mode each map contains bit mapped data and the maps are addressed together to provide color signals from which color video signals are derived. In the second mode, one map contains character representing data and a further map, character display dot patterns. In this mode the first map is addressed to provide partial addresses for the further map. These partial addresses are combined with row scan data signals to access the further map from which the character display dot data is used to generate the video signals.

公开(公告)号：AU4254985A

公开(公告)日：1986-01-23

申请号：AU4254985

申请日：1985-05-16

Applicant: IBM

Inventor： RACKLEY DARWIN P ,  SAENZ JESUS A ,  YOSIM PAUL S

IPC: G09G5/18 ,  G06F3/153 ,  G09G1/16 ,  G09G1/28 ,  G09G5/00 ,  G09G5/02 ,  G09G5/04 ,  G09G5/36 ,  H04N3/27 ,  H04N3/32 ,  H04N5/46

Abstract: A digital display system includes a monitor arranged to receive digital display data and synchronising signals to develop displays on a cathode ray tube. The monitor is switched between different line structure and/or colour definition modes in response to the polarity of one of the vertical or horizontal synchronising signals trains. A circuit receives this train to provide control signals to the horizontal time base and/or a colour signal code converter. The time base control signal, in accordance with its binary value, controls the frequency of the time base. The colour converter, in response to the control signals, either passes colour signals received in parallel over six input lines without change to the cathode ray tube drive circuits or converts colour signals on four of the input lines to output signals on the six lines to the drive circuits.

公开(公告)号：GB2104356A

公开(公告)日：1983-03-02

申请号：GB8222696

申请日：1982-08-06

Applicant: IBM

Inventor： SAENZ JESUS A

IPC: G06F3/153 ,  G06T11/00 ,  G09G5/02

Abstract: In e.g. a personal computer an 8-bit character byte is fetched from a random access memory (30) for each character and applied to a character generator (28). An associated 8-bit attribute bit is also fetched from the random access memory (30) and applied to the inputs of a multiplexer (32). Four of the attribute bits designate the color of the character to be displayed on raster CRT (eg TV) (14). The remaining four attribute bits designate the background color of the character. The eight attribute bits are selectively gated to the outputs of the multiplexer (32) under the control of character serial dots from the parallel-to-serial converter (34) as red (R), green (G) and blue (B) digital color signals which are applied to a composite video signal generator (38). The colors of the font and background of each individual character are thus independently controlled. They may be identical, causing the character to be invisible.