公开(公告)号：JPH05218348A

公开(公告)日：1993-08-27

申请号：JP28689292

申请日：1992-10-01

Applicant: IBM

Inventor： SAN FUU DONGU ,  UEI WANGU

IPC: H01L27/10 ,  H01L21/8242 ,  H01L27/108

Abstract: PURPOSE: To reduce a parasitic capacitance and to eliminate noise by forming a pair of bit lines of a first set on a first insulating layer by forming a pair of bit lines of a second set to pile a second insulating layer on the first insulating layer for offsetting in a lateral direction and by making each to comprise mutually connecting layers. CONSTITUTION: First conductive first plural conductive bit-line pairs 32 and 32' which extend to a first direction are arranged on a first insulating layer of a substrate, having plural drain-junction regions with intervals in a surface. First and second conductive second plural conductive bit-line pairs 34 and 34' are arranged offset, in a lateral direction on a second layer arranged thereon. A first plural electrical conductive contact means which extend from a first selected drain-junction region to the first bit line 32 and a second plural electrical conductive contact means, which extends from a second selected drain- junction region to the second bit-line 34', are provided.