公开(公告)号：GB2529221A

公开(公告)日：2016-02-17

申请号：GB201414424

申请日：2014-08-14

Applicant: IBM

Inventor： SAUTTER ROLF ,  SAPP GORDON B ,  DARLA ANANTHNAG R ,  PATAVARDHAN PRAVEEN

IPC: G11C15/04 ,  G06F17/30 ,  G11C11/418 ,  G11C11/419

Abstract: Content addressable memory cell, (CAM) comprising a first memory cell 108, a first compare circuitry 109, and a first logic circuitry 111, the first logic circuitry comprising a first n-type field effect transistor (n-FET) T16, a first p-type field effect transistor (p-FET) T15, and a first input terminal 128). The first compare circuitry is communicatively coupled to the first memory cell 108 via a first communicative coupling 106, 107 enabling transmitting first data stored in the first memory cell to the first compare circuitry 109, wherein the first input terminal128 is communicatively coupled via a second communicative coupling 110 to the first compare logic 109, wherein a gate of the first n-FET T16 and a gate of the first p-FET T15 are galvanically coupled to the first input terminal. Galvanic coupling includes wiring elements made of heavily/degenerately doped semiconductor, metals, or metal nitrides. Communicative coupling includes galvanic couplings as well as transistors, logical gates, or functional digital blocks, between terminals. Claims are also made to a method of operation, and to implementation of the circuit on a semiconductor wafer. Claims are also made to a Hardware Description Language description for the circuits. Other embodiments include two or three separate CAM circuits co-joined by logic circuits (see 118, 111 figures 9 -11), the CAM circuits also preferably using data masking. Dynamic or clocked logic gates may also be employed.