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    METHOD FOR MERGING DATA ON A TWO TAPE DRIVE SYSTEM
    3.
    发明专利
    METHOD FOR MERGING DATA ON A TWO TAPE DRIVE SYSTEM 未知

    公开(公告)号：CA968060A

    公开(公告)日：1975-05-20

    申请号：CA147822

    申请日：1972-07-25

    Applicant: IBM

    Inventor： SCHLOSS PHILLIP C

    IPC: G06F7/32

    Abstract: Records from tapes one and two are merged in a logical sequence on tape three in a two-tape drive system. Prior to the merge operation sequence, control bits, ones and zeros, developed in response to high, low, equal comparisons of the records on tapes one and two, are stored. Then in two successive operations, records, first from tape one and then from tape two, are written on tape three, in sequence as determined by the control bits. While records from tape one are being written, control bits indicating that records from tape two are next in sequence cause zeros to be written on tape three to reserve space for records from tape two. After all records have been written from tape one and zeros have been written to reserve space for records from tape two, a tape mark is written on tape three and tapes one and three are rewound. Tape two is mounted in place of tape one and whenever zeros are read from tape three, records from tape two are inserted. When the tape mark on either tape two or three is detected, the operation is complete.

    MEMORY ACCESS DEVICE
    4.
    发明专利
    MEMORY ACCESS DEVICE 未知

    公开(公告)号：CA1001315A

    公开(公告)日：1976-12-07

    申请号：CA170060

    申请日：1973-04-24

    Applicant: IBM

    Inventor： DUMSTORFF EUGENE F ,  IVERSON JOHN H ,  SCHLOSS PHILLIP C ,  WONG PHILIP C

    IPC: G06F12/02 ,  G06F3/14 ,  G06F3/153 ,  G09G1/18

    Abstract: The specification describes a memory access technique wherein a display or other controlled device accesses sequential locations in memory without control unit intervention following an initial address and a selection of operating mode. An interfaced display continously displays data, status, prompting and/or operator guidance information from selected memory locations independent of the system control unit following mode select and an initial address. The display as shown includes a wiggle sweep cathode ray tube display controlled by a series of counters.

    LINE PRINTER ATTACHMENT
    7.
    发明专利
    LINE PRINTER ATTACHMENT 未知

    公开(公告)号：CA1180461A

    公开(公告)日：1985-01-02

    申请号：CA417819

    申请日：1982-12-15

    Applicant: IBM

    Inventor： REGEHR JOHN L ,  SCHLOSS PHILLIP C

    IPC: G06F3/12 ,  G06F3/153 ,  G06K15/00

    Abstract: A line printer attachment for converting a display screen copier printer to a line printer. The last or extra line of the display is used as the line print buffer. An initiate print signal is generated upon detecting that the last or extra line is to be scanned. The initiate print signal is used to blank or inhibit the serial video data from the display screen and to enable the printer. The serial video data is constantly sent to the printer attachment but is ignored until the printer is enabled. With the printer enabled, printing takes place using the line print buffer data which has been serialized as serial video data. The print buffer data remains unchanged during the entire printing of the line where the printing is done in series of horizontal lines to complete the printing of a line At the end of each horizontal line of print a vertical screen retrace occurs and the display screen is swept where again the last or extra line is detected and another initiate print signal is generated. The next horizontal line of the series of horizontal lines fox completing a line of print is printed and the operation repeats until an entire line of printing is completed.

    MICROPROCESSOR SYSTEM
    8.
    发明专利
    MICROPROCESSOR SYSTEM 未知

    公开(公告)号：CA1091355A

    公开(公告)日：1980-12-09

    申请号：CA277472

    申请日：1977-05-03

    Applicant: IBM

    Inventor： HEUER DALE A ,  SCHLOSS PHILLIP C ,  SCHROEDER LARRY L

    IPC: G06F7/38 ,  G06F7/00 ,  G06F7/50 ,  G06F7/508 ,  G06F9/22 ,  G06F9/30 ,  G06F12/00 ,  G06F12/06 ,  G06F15/16 ,  G06F15/177 ,  G06F15/78 ,  G06F13/00

    Abstract: MICROPROCESSOR SYSTEM A single chip large scale integration processor processes its own on-chip control storage array while including the ability to also address supplemental off-chip control storage and to use such off-chip supplemental storage in substitution for portions of the on-chip storage. The processor further includes simplified arithmetic and logic (ALU) circuitry wherein the adder circuit has portions selectively gated to perform other functions with a reduced logic circuit requirement. Processor function is also enhanced by providing a read only storage (ROS) array in association with the ALU to provide multiple register loading and control functions in response to certain addresses. The processor also includes memory control circuitry that permits a group of like processors to access a single, external memory on a dynamic, prioritized basis.

    MICROPROCESSOR SYSTEM
    9.
    发明专利
    MICROPROCESSOR SYSTEM 未知

    公开(公告)号：CA1103367A

    公开(公告)日：1981-06-16

    申请号：CA347889

    申请日：1980-03-18

    Applicant: IBM

    Inventor： HEUER DALE A ,  SCHLOSS PHILLIP C ,  SCHROEDER LARRY L

    IPC: G06F13/00

    Abstract: MICROPROCESSOR SYSTEM A single chip large scale integration processor processes its own on-chip control storage array while including the ability to also address supplemental off-chip control storage and to use such off-chip supplemental storage in substitution for portions of the on-chip storage. The processor further includes simplified arithmetic and logic (ALU) circuitry wherein the adder circuit has portions selectively gated to perform other functions with a reduced logic circuit requirement. Processor function is also enhanced by providing a read only storage (ROS) array in association with the ALU to provide multiple register loading and control functions in response to certain addresses. The processor also includes memory control circuitry that permits a group of like processors to access a single, external memory on a dynamic, prioritized basis.

    MICROPROCESSOR SYSTEM
    10.
    发明专利
    MICROPROCESSOR SYSTEM 未知

    公开(公告)号：CA1092713A

    公开(公告)日：1980-12-30

    申请号：CA347890

    申请日：1980-03-18

    Applicant: IBM

    Inventor： HEUER DALE A ,  SCHLOSS PHILLIP C ,  SCHROEDER LARRY L

    IPC: G06F13/00

    Abstract: MICROPROCESSOR SYSTEM A single chip large scale integration processor processes its own on-chip control storage array while including the ability to also address supplemental off-chip control storage and to use such off-chip supplemental storage in substitution for portions of the on-chip storage. The processor further includes simplified arithmetic and logic (ALU) circuitry wherein the adder circuit has portions selectively gated to perform other functions with a reduced logic circuit requirement. Processor function is also enhanced by providing a read only storage (ROS) array in association with the ALU to provide multiple register loading and control functions in response to certain addresses. The processor also includes memory control circuitry that permits a group of like processors to access a single, external memory on a dynamic, prioritized basis.

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