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    Computer system and information transmission method
    2.
    发明专利
    Computer system and information transmission method 未知

    公开(公告)号：CZ9603197A3

    公开(公告)日：2002-06-12

    申请号：CZ319796

    申请日：1994-12-27

    Applicant: IBM

    Inventor： SHIPPY DAVID JAMES ,  SHULER DAVID BENJAMIN

    IPC: G06F12/08

    Abstract: A memory system wherein data retrieval is simultaneously initiated in both and L2 cache and main memory, which allows memory latency associated with arbitration, memory DRAM address translation, and the like to be minimized in the event that the data sought by the processor is not in the L2 cache (miss). The invention allows for any memory access to be interrupted in the storage control unit prior to any memory signals being activated. The L2 and memory access controls are in a single component, i.e. the storage control unit (SCU). Both the L2 and the memory have a unique port into the CPU which allows data to be directly transferred. This eliminates the overhead associated with storing the data in an intermediate device, such as a cache or memory controller.

    3.
    发明专利
    未知

    公开(公告)号：BR9502022A

    公开(公告)日：1996-01-30

    申请号：BR9502022

    申请日：1995-05-11

    Applicant: IBM

    Inventor： SHIPPY DAVID JAMES ,  SHULER DAVID BENJAMIN

    IPC: G06F12/08 ,  G06F12/00

    Abstract: A memory system wherein data retrieval is simultaneously initiated in both and L2 cache and main memory, which allows memory latency associated with arbitration, memory DRAM address translation, and the like to be minimized in the event that the data sought by the processor is not in the L2 cache (miss). The invention allows for any memory access to be interrupted in the storage control unit prior to any memory signals being activated. The L2 and memory access controls are in a single component, i.e. the storage control unit (SCU). Both the L2 and the memory have a unique port into the CPU which allows data to be directly transferred. This eliminates the overhead associated with storing the data in an intermediate device, such as a cache or memory controller.

    COMPUTER SYSTEM, AS WELL AS METHOD OF TRANSMITTING INFORMATION FROM THE EXTERNAL CACHE AND THE MAIN MEMORY TO THE PROCESSOR OF THE COMPUTER SYSTEM
    5.
    发明专利
    COMPUTER SYSTEM, AS WELL AS METHOD OF TRANSMITTING INFORMATION FROM THE EXTERNAL CACHE AND THE MAIN MEMORY TO THE PROCESSOR OF THE COMPUTER SYSTEM 未知

    公开(公告)号：HUT76241A

    公开(公告)日：1997-07-28

    申请号：HU9603142

    申请日：1994-12-27

    Applicant: IBM

    Inventor： SHIPPY DAVID JAMES ,  SHULER DAVID BENJAMIN

    IPC: G06F12/08

    Abstract: A memory system wherein data retrieval is simultaneously initiated in both and L2 cache and main memory, which allows memory latency associated with arbitration, memory DRAM address translation, and the like to be minimized in the event that the data sought by the processor is not in the L2 cache (miss). The invention allows for any memory access to be interrupted in the storage control unit prior to any memory signals being activated. The L2 and memory access controls are in a single component, i.e. the storage control unit (SCU). Both the L2 and the memory have a unique port into the CPU which allows data to be directly transferred. This eliminates the overhead associated with storing the data in an intermediate device, such as a cache or memory controller.

    INTEGRATED SECOND-LEVEL CACHE MEMORY AND MEMORY CONTROLLER WITH MULTIPLE-ACCESS DATA PORTS
    6.
    发明专利
    INTEGRATED SECOND-LEVEL CACHE MEMORY AND MEMORY CONTROLLER WITH MULTIPLE-ACCESS DATA PORTS 未知

    公开(公告)号：PL316998A1

    公开(公告)日：1997-03-03

    申请号：PL31699894

    申请日：1994-12-27

    Applicant: IBM

    Inventor： SHIPPY DAVID JAMES ,  SHULER DAVID BENJAMIN

    IPC: G06F12/08

    Abstract: A memory system wherein data retrieval is simultaneously initiated in both and L2 cache and main memory, which allows memory latency associated with arbitration, memory DRAM address translation, and the like to be minimized in the event that the data sought by the processor is not in the L2 cache (miss). The invention allows for any memory access to be interrupted in the storage control unit prior to any memory signals being activated. The L2 and memory access controls are in a single component, i.e. the storage control unit (SCU). Both the L2 and the memory have a unique port into the CPU which allows data to be directly transferred. This eliminates the overhead associated with storing the data in an intermediate device, such as a cache or memory controller.

    INTEGRATED LEVEL TWO CACHE AND MEMORY CONTROLLER WITH MULTIPLE DATA PORTS
    7.
    发明专利
    INTEGRATED LEVEL TWO CACHE AND MEMORY CONTROLLER WITH MULTIPLE DATA PORTS 未知

    公开(公告)号：HU9603142D0

    公开(公告)日：1997-01-28

    申请号：HU9603142

    申请日：1994-12-27

    Applicant: IBM

    Inventor： SHIPPY DAVID JAMES ,  SHULER DAVID BENJAMIN

    IPC: G06F12/08

    Abstract: A memory system wherein data retrieval is simultaneously initiated in both and L2 cache and main memory, which allows memory latency associated with arbitration, memory DRAM address translation, and the like to be minimized in the event that the data sought by the processor is not in the L2 cache (miss). The invention allows for any memory access to be interrupted in the storage control unit prior to any memory signals being activated. The L2 and memory access controls are in a single component, i.e. the storage control unit (SCU). Both the L2 and the memory have a unique port into the CPU which allows data to be directly transferred. This eliminates the overhead associated with storing the data in an intermediate device, such as a cache or memory controller.

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