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公开(公告)号：CZ9702257A3
公开(公告)日：1998-03-18
申请号：CZ225797
申请日：1996-01-19
Applicant: IBM
Inventor： BEERS GREGORY EDWARD , FRANKENY RICHARD FRANCIS , SMADI MITHKAL MOH D
CPC classification number: H04L25/0292 , H04L5/1423 , H04L25/0278 , H04L25/028
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公开(公告)号：CA2206246A1
公开(公告)日：1996-08-01
申请号：CA2206246
申请日：1996-01-19
Applicant: IBM
Inventor： FRANKENY RICHARD FRANCIS , SMADI MITHKAL MOH D , BEERS GREGORY EDWARD
IPC: G06F3/00 , H04L5/14 , H04L25/02 , H03K19/0175
Abstract: A method and apparatus are disclosed for sending and receiving logic signals. A driver is connected to a first end of a transmission line with a predetermined impedance and first and second transmission line ends for communicating the logic signals. The driver has a source for sending the logic signals, and a reference generator connected to the source for setting the magnitude of the signals sent by the source. A receiver is connected to the second transmission line end, and has a transmission line terminator for sinking the signals, and a reference generator connected to the terminator for setting a bias of the terminator to establish a certain family of terminator impedance for sinking the signals. The driver reference generator and the receiver reference generator interactively match the terminator impedance to the transmission line for the set magnitude of the signals.
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Patent Agency Ranking
公开(公告)号：CZ290426B6
公开(公告)日：2002-07-17
申请号：CZ225797
申请日：1996-01-19
Applicant: IBM
Inventor： BEERS GREGORY EDWARD , FRANKENY RICHARD FRANCIS , SMADI MITHKAL MOH D
Abstract: A method and apparatus are disclosed for sending and receiving logic signals. A logic signal driver (20A) is connected to a first end of a transmission line (24) with predetermined impedance and first and second transmission line (24) ends for communicating the logic signals. The logic signal driver (20A) has a source (12) for sending the logic signals, and a reference generator (10) connected to the source (12) for setting the magnitude of the signals sent by the source (12). A logic signal receiver (20B) is connected to the second transmission line (24) end, and has a transmission line terminator (14) for sinking the signals, and a reference generator (10) connected to the terminator (14) for setting a bias of the terminator (12) to establish a certain family of terminator (14) impedances for sinking the signals. The logic signal driver (20A) reference generator (10B) and the logic signal receiver (20B) reference generator (10B) interactively match the terminator (14) impedance to the transmission line (24) for the set magnitude of the signals.
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公开(公告)号：CZ225797A3
公开(公告)日：1998-03-18
申请号：CZ225797
申请日：1996-01-19
Applicant: IBM
Inventor： BEERS GREGORY EDWARD , FRANKENY RICHARD FRANCIS , SMADI MITHKAL MOH D
Abstract: A method and apparatus are disclosed for sending and receiving logic signals. A driver is connected to a first end of a transmission line with a predetermined impedance and first and second transmission line ends for communicating the logic signals. The driver has a source for sending the logic signals, and a reference generator connected to the source for setting the magnitude of the signals sent by the source. A receiver is connected to the second transmission line end, and has a transmission line terminator for sinking the signals, and a reference generator connected to the terminator for setting a bias of the terminator to establish a certain family of terminator impedances for sinking the signals. The driver reference generator and the receiver reference generator interactively match the terminator impedance to the transmission line for the set magnitude of the signals.
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公开(公告)号：PL323192A1
公开(公告)日：1998-03-16
申请号：PL32319296
申请日：1996-02-23
Applicant: IBM
Inventor： BEERS GREGORY EDWARD , FRANKENY RICHARD FRANCIS , SMADI MITHKAL MOH D
Abstract: A method and apparatus are disclosed for sending and receiving logic signals responsive to external digital data input and control signals. A reference circuit providing a first and second reference signal is common to the signal generating and receiving circuitry. The signal generating circuitry includes a signal source connected to the transmission line for generating a variable level digital signal, and a reference level adjusting and switching circuit ("RLA/S circuit") which is responsive to the digital data input and the first reference signal. The RLA/S circuit is connected to the signal source for selecting the level of the variable level digital signal and providing a switching signal. The signal source output is thus adjusted and switched so that the signal source generates a digital signal to the transmission line which follows the digital data input at the selected output signal level. The signal receiving circuitry includes a variable input impedance circuit connected to the transmission line which is responsive to the second reference signal for receiving variable level digital signals from the transmission line. It also includes a detecting circuit connected to receive the variable level digital signals from the variable input impedance circuit. The detecting circuit is responsive to the first reference signal and detects logic states of the variable level digital signals as determined by the first reference signal. The detecting circuit also converts the detected logic states into corresponding logic signals of predetermined output levels.
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公开(公告)号：PL321324A1
公开(公告)日：1997-12-08
申请号：PL32132496
申请日：1996-01-19
Applicant: IBM
Inventor： BEERS GREGORY EDWARD , FRANKENY RICHARD FRANCIS , SMADI MITHKAL MOH D
Abstract: A method and apparatus are disclosed for sending and receiving logic signals. A driver is connected to a first end of a transmission line with a predetermined impedance and first and second transmission line ends for communicating the logic signals. The driver has a source for sending the logic signals, and a reference generator connected to the source for setting the magnitude of the signals sent by the source. A receiver is connected to the second transmission line end, and has a transmission line terminator for sinking the signals, and a reference generator connected to the terminator for setting a bias of the terminator to establish a certain family of terminator impedances for sinking the signals. The driver reference generator and the receiver reference generator interactively match the terminator impedance to the transmission line for the set magnitude of the signals.
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公开(公告)号：CA2216367A1
公开(公告)日：1996-11-14
申请号：CA2216367
申请日：1996-02-23
Applicant: IBM
Inventor： FRANKENY RICHARD FRANCIS , BEERS GREGORY EDWARD , SMADI MITHKAL MOH D
Abstract: A method and apparatus are disclosed for sending and receiving logic signals responsive to external digital data input and control signals. A reference circuit (10, 22) providing a first and second reference signal is common to the signal generating and receiving circuitry. The signal generating circuitry includes a signal source (12) connected to a transmission line (24) for generating a variable level digital signal, and a reference level adjusting and switching circuit ("RLA/S circuit") (10) which is responsive to the digital data input and the first reference signal. The RLA/S circuit is connected to the signal source for selecting the level of the variable level digital signal and providing a switching signal. The signal source output is thus adjusted and switched so that the signal source generates a digital signal to the transmission line which follows the digital data input at the selected output signal level. The signal receiving circuitry includes a variable input impedance circuit (14) connected to the transmission line which is responsive to the second reference signal for receiving variable level digital signals from the transmission line. It also includes a detecting (14, 16) circuit connected to receive the variable level digital signals from the variable input impedance circuit. The detecting circuit is responsive to the first reference signal and detects logic states of the variable level digital signals as determined by the first reference signal. The detecting circuit also converts the detected logic states into corresponding logic signals of predetermined output levels.
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