公开(公告)号：GB2505823A

公开(公告)日：2014-03-12

申请号：GB201322155

申请日：2012-04-11

Applicant: IBM

Inventor： RIVERS JUDE A ,  SRINVASAN VIJAYALAKSHMI

IPC: G11C29/52 ,  G06F11/10 ,  G11C29/00 ,  G11C29/02

Abstract: Multi-bit stuck-at fault error recovery can be enabled by adaptive multi-bit error correction method, in which the overhead of error correction hardware is reduced without affecting the lifetime of the memory device. Error correction logic hardware is decoupled from memory blocks. An error correction logic block is partitioned such that error correction logic entries support different number of error correction capabilities based on the probability of occurrence of the different number of errors in different memory blocks. Faulty memory blocks are mapped to appropriate error correction logic entries. The mapping can be one-to-one or many-to-one depending on embodiments. The adaptive partitioning of the error correction logic entries can be configured to match projected statistical distribution of errors in logic blocks, and can reduce the total error correction logic overhead, provide sufficient error correction, and/or extend the lifetime of the memory device.

公开(公告)号：GB2505823B

公开(公告)日：2014-11-19

申请号：GB201322155

申请日：2012-04-11

Applicant: IBM

Inventor： RIVERS JUDE A ,  SRINVASAN VIJAYALAKSHMI

IPC: G11C29/52 ,  G06F11/10 ,  G11C29/00 ,  G11C29/02

Abstract: Multi-bit stuck-at fault error recovery can be enabled by adaptive multi-bit error correction method, in which the overhead of error correction hardware is reduced without affecting the lifetime of the memory device. Error correction logic hardware is decoupled from memory blocks. An error correction logic block is partitioned such that error correction logic entries support different number of error correction capabilities based on the probability of occurrence of the different number of errors in different memory blocks. Faulty memory blocks are mapped to appropriate error correction logic entries. The mapping can be one-to-one or many-to-one depending on embodiments. The adaptive partitioning of the error correction logic entries can be configured to match projected statistical distribution of errors in logic blocks, and can reduce the total error correction logic overhead, provide sufficient error correction, and/or extend the lifetime of the memory device.