1.
    发明专利
    未知

    公开(公告)号:DE69504918T2

    公开(公告)日:1999-05-27

    申请号:DE69504918

    申请日:1995-06-16

    Applicant: IBM

    Abstract: The present system may be utilized to minimize access performance penalties in memory subsystems which utilize redundant arrays of disk memory devices. Redundant arrays of disk memory devices provide levels of reliability which are not available with single storage devices; however, the redundancy carries with it an access performance degradation due to the requirement that such systems write data segments and parity elements to the array each time an application updates data within the system. A large nonvolatile cache is therefore provided in association with a redundant array of disk memory devices. Each time a data segment is written or read the data segment is staged from the array to the nonvolatile cache, if the data segment is not already within the cache. Additionally, if the operation is an update, a parity element associated with the data segment to be updated is also staged to the cache with the existing data segment content. An updated parity element is then calculated based upon the updated data, the existing data and the existing parity element. Data segments and associated parity elements are then maintained in the cache for future reading and updates until the number of updated data segments within the cache exceeds a predetermined value. Thereafter, selected data segments and associated parity elements are destaged from the cache to the array based upon a "Least Recently Utilized" (LRU) or "minimum seek" algorithm.

    2.
    发明专利
    未知

    公开(公告)号:DE69504918D1

    公开(公告)日:1998-10-29

    申请号:DE69504918

    申请日:1995-06-16

    Applicant: IBM

    Abstract: The present system may be utilized to minimize access performance penalties in memory subsystems which utilize redundant arrays of disk memory devices. Redundant arrays of disk memory devices provide levels of reliability which are not available with single storage devices; however, the redundancy carries with it an access performance degradation due to the requirement that such systems write data segments and parity elements to the array each time an application updates data within the system. A large nonvolatile cache is therefore provided in association with a redundant array of disk memory devices. Each time a data segment is written or read the data segment is staged from the array to the nonvolatile cache, if the data segment is not already within the cache. Additionally, if the operation is an update, a parity element associated with the data segment to be updated is also staged to the cache with the existing data segment content. An updated parity element is then calculated based upon the updated data, the existing data and the existing parity element. Data segments and associated parity elements are then maintained in the cache for future reading and updates until the number of updated data segments within the cache exceeds a predetermined value. Thereafter, selected data segments and associated parity elements are destaged from the cache to the array based upon a "Least Recently Utilized" (LRU) or "minimum seek" algorithm.

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