公开(公告)号：GB2582497B

公开(公告)日：2022-07-06

申请号：GB202008475

申请日：2018-11-22

Applicant: IBM

Inventor： STEVEN CARLOUGH ,  SUSAN MARIE EICKHOFF ,  STEPHEN POWELL ,  JIE ZHENG ,  GARY VAN HUBEN ,  PATRICK JAMES MEANEY

IPC: G06F12/08 ,  G06F13/38

Abstract: One or more memory systems, architectural structures, and/or methods of storing information in memory devices is disclosed to improve the data bandwidth and or to reduce the load on the communications links in a memory system. The system may include one or more memory devices, one or more memory control circuits and one or more data buffer circuits. In one embodiment, the Host only transmits data over its communications link with the data buffer circuit. In one aspect, the memory control circuit does not send a control signal to the data buffer circuits. In one aspect, the memory control circuit and the data buffer circuits each maintain a separate state machine-driven address pointer or local address sequencer, which contains the same tags in the same sequence. In another aspect, a resynchronization method is disclosed.

公开(公告)号：GB2570041A

公开(公告)日：2019-07-10

申请号：GB201818693

申请日：2018-11-16

Applicant: IBM

Inventor： STEPHEN POWELL ,  VENKATA TAVVA ,  DHARMESH PARIKH

IPC: G11C7/22 ,  G06F13/16 ,  G11C11/4063

Abstract: A method of managing DRAM including: tracking an operating state of each DRAM bank in a rank; tracking a quantity of outstanding CAS commands (e.g. column select commands such as Column Access Strobe or Column Address Signal) in a request queue (e.g. a read or write queue) in relation to the tracked operating state of each bank (e.g. active, idle, waiting for a CAS command), wherein the outstanding CAS commands include those under-service and those waiting for service; for each cycle, identifying the tracked quantity of CAS commands waiting for service in a selected queue, and assessing this quantity in view of a predefined ratio; and individually controlling the operating state of each of the banks based on the assessment, including delaying activation of an idle bank wherein the idle state consumes less power than the active state. There is also a computer program product and computer system for implementing the method, the computer system including a processing unit and memory controller operatively couple to the DRAM. The memory controller may restrict the quantity of active banks for the current cycle.

公开(公告)号：GB2570041B

公开(公告)日：2020-12-02

申请号：GB201818693

申请日：2018-11-16

Applicant: IBM

Inventor： STEPHEN POWELL ,  VENKATA TAVVA ,  DHARMESH PARIKH

IPC: G11C7/22 ,  G06F9/30 ,  G06F13/16 ,  G11C11/4063 ,  G11C11/4072 ,  G11C11/4076 ,  G11C11/4096

Abstract: A system, method, and computer program product are provided herein to manage DRAM bank activation per cycle. A memory controller with embedded scheduling logic is employed to manage the system, method, and computer program product and to restrict the quantity of active banks in a given cycle, resulting in power savings with minimal performance loss, if any. The scheduling logic provides instructions to manage the state of associated DRAM banks. Each bank is either in an idle state or an active state, with the idle state consuming less power than the active state. The scheduling logic restricts the quantity of active banks in any cycle, with all other banks being in an idle state, which provides power savings to the associated system.

公开(公告)号：GB2582497A

公开(公告)日：2020-09-23

申请号：GB202008475

申请日：2018-11-22

Applicant: IBM

Inventor： STEVEN CARLOUGH ,  SUSAN EICKHOFF ,  STEPHEN POWELL ,  JIE ZHENG ,  GARY VAN HUBEN ,  PATRICK JAMES MEANEY

IPC: G06F12/08 ,  G06F13/38

Abstract: One or more memory systems, architectural structures, and/or methods of storing information in memory devices is disclosed to improve the data bandwidth and or to reduce the load on the communications links in a memory system. The system may include one or more memory devices, one or more memory control circuits and one or more data buffer circuits. In one embodiment, the Host only transmits data over its communications link with the data buffer circuit. In one aspect, the memory control circuit does not send a control signal to the data buffer circuits. In one aspect, the memory control circuit and the data buffer circuits each maintain a separate state machine-driven address pointer or local address sequencer, which contains the same tags in the same sequence. In another aspect, a resynchronization method is disclosed.