公开(公告)号：DE69230093T2

公开(公告)日：2000-04-13

申请号：DE69230093

申请日：1992-10-27

Applicant: IBM

Inventor： COLEMAN JOHN JOSEPH ,  COLEMAN RONALD GERALD ,  MONROE OWEN KEITH ,  STUCKE ROBERT FREDERICK ,  VANDERBECK ELIZABETH ANNE ,  BELLO STEPHEN EDWARD ,  HATTERSLEY JOHN ROBERT ,  HUA KIEN ANH ,  PRUETT DAVID RAYMOND ,  ROLLO GERALD FRANKLIN

IPC: G06F15/16 ,  G06F15/173

公开(公告)号：DE69518782D1

公开(公告)日：2000-10-19

申请号：DE69518782

申请日：1995-01-25

Applicant: IBM

Inventor： SETHU HARISH ,  STUCKE ROBERT FREDERICK ,  STUNKEL CRAIG BRIAN

IPC: G06F15/173 ,  H04L12/56 ,  G06F15/16

Abstract: The technique for deadlock free routing through a multi-stage cross-point packet switch involves defining several prescribed routes through the network such that a packet can be carried from individual nodes within the nodes over different corresp. routes to every other node within the nodes. Each defined routes extends over at least one link. The prescribed routes is defined so as to parse the network into two partitions connected to respectively two groups of differing nodes, such that packets that are to transit between two nodes in the first group and connected solely to the first network partition would not be carried over any route having a link extending into the second network partition. All of the prescribed routes are stored in a resulting route table.

公开(公告)号：DE69230093D1

公开(公告)日：1999-11-11

申请号：DE69230093

申请日：1992-10-27

Applicant: IBM

Inventor： COLEMAN JOHN JOSEPH ,  COLEMAN RONALD GERALD ,  MONROE OWEN KEITH ,  STUCKE ROBERT FREDERICK ,  VANDERBECK ELIZABETH ANNE ,  BELLO STEPHEN EDWARD ,  HATTERSLEY JOHN ROBERT ,  HUA KIEN ANH ,  PRUETT DAVID RAYMOND ,  ROLLO GERALD FRANKLIN

IPC: G06F15/16 ,  G06F15/173

公开(公告)号：DE69304359D1

公开(公告)日：1996-10-10

申请号：DE69304359

申请日：1993-01-27

Applicant: IBM

Inventor： STUCKE ROBERT FREDERICK

IPC: H01R12/16 ,  H05K1/14 ,  H05K3/36 ,  H05K7/14 ,  H05K7/10

Abstract: A high density interconnection system for connecting large numbers of unique signal lines between orthogonally positioned circuit cards, utilizes pins (12) from the back of a zero insertion force connector (ZIF) (14) to extend through the interconnection card (10) and mate with a female socket connector (20) on a second circuit board (24). Pins from the ZIF connector which are not aligned with the sockets of the orthogonally positioned socket connector may be connected to pins on the interconnection card which are aligned with the socket connector but not the ZIF. Very high numbers of connections between circuit cards may be made in a small volume and maintain signal line length at a minimum to ensure maximum signal transfer speed.