公开(公告)号：JP2005182434A

公开(公告)日：2005-07-07

申请号：JP2003421942

申请日：2003-12-19

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： TANIGUCHI MASAYOSHI

IPC: G01R31/28 ,  G06F11/00 ,  G06F11/22 ,  G06F12/14 ,  G06F15/78

CPC classification number: G01R31/31705 ,  G01R31/318536 ,  G01R31/318555 ,  G06F21/79 ,  G06F21/85 ,  G06F2221/2105 ,  G06F2221/2149 ,  G11C7/24 ,  G11C2029/0401 ,  G11C2029/0407 ,  G11C2029/3202

Abstract: PROBLEM TO BE SOLVED: To surely prevent access to a memory protected area when an invasion into the inside of an SoC is made from the outside, and make the execution of debugging by a boundary scan test possible. SOLUTION: A microcomputer is provided with; a TAP controller 120 which monitors input to a processor 111 from the outside; an instruction decoder 131; inner registers 141 and 142 which monitor whether access destination addresses for the access by the processor 111 to a ROM 113 and an SRAM 114 exist in a preliminarily fixed protected area; comparators 143 and 144; inner registers 145 and 146 which are access control means; and multiplexers 147 and 149. When control instructions to the processor 111 are detected and also the access to the protected area from the processor 111 is detected, the access destination addresses are replaced with the addresses of the ROM 201 and SRAM 202 of an additional circuit block 200 prepared by a developer. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：当从外部进入SoC内部时，确实防止访问存储器保护区域，并且可以通过边界扫描测试来执行调试。

解决方案：提供微型计算机; TAP控制器120，其从外部监视对处理器111的输入; 指令译码器131; 内部寄存器141和142，其监视由处理器111访问ROM 113和SRAM 114的访问目的地址是否存在于预先固定的保护区域中; 比较者143和144; 作为访问控制装置的内部寄存器145和146; 和多路复用器147和149.当检测到对处理器111的控制指令并且还检测到来自处理器111的保护区域的访问时，将访问目的地地址替换为附加电路的ROM 201和SRAM 202的地址 块200由开发者准备。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2005190112A

公开(公告)日：2005-07-14

申请号：JP2003429853

申请日：2003-12-25

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： TANIGUCHI MASAYOSHI

IPC: G06F11/22 ,  G01R31/317 ,  G06F11/267 ,  G06F15/78

CPC classification number: G06F11/267 ,  G01R31/31705

Abstract: PROBLEM TO BE SOLVED: To debug by reading or rewriting contents of an arbitrary register in an SoC by an an LSSD scan test. SOLUTION: The SoC is provided with a scan chain in which a plurality of latch circuits are connected like a chain and which executes a scan test and a debug circuit 100 for designating the specific latch circuit configuring the scan chain for reading data while executing the scan test to the scan chain. The scan chain configures a feedback loop by returning the output to the input of the leading latch circuit. Also, there are a plurality of scan chains, and each scan chains is configured of the same number of latch circuits, and provided with the latch circuit for executing the scan test and the dummy latch circuit for arranging the number of the latch circuits configuring the scan chain. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：通过LSSD扫描测试读取或重写SoC中的任意寄存器的内容进行调试。 解决方案：SoC提供有扫描链，其中多个锁存电路如链状连接并执行扫描测试，调试电路100用于指定配置用于读取数据的扫描链的特定锁存电路，同时 对扫描链执行扫描测试。 扫描链通过将输出返回到前导锁存电路的输入来配置反馈回路。 此外，存在多条扫描链，并且每条扫描链由相同数量的锁存电路构成，并且具有用于执行扫描测试的锁存电路和用于布置构成扫描测试的锁存电路的数量的虚拟锁存电路 扫描链。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JPH09179812A

公开(公告)日：1997-07-11

申请号：JP32547695

申请日：1995-12-14

Applicant: IBM

Inventor： YANAGISAWA TAKASHI ,  TANIGUCHI MASAYOSHI ,  NAKANO MASATAKE

IPC: G06F13/28

Abstract: PROBLEM TO BE SOLVED: To provide a system where DMA transfer is correctly executed even when DMA controllers exist in a self system and also in a docking station by adding the respective specified first and second DAM controllers and a control circuit. SOLUTION: This system includes a first and second DMA controllers where prescribed IO addresses are respectively assigned and the control circuit which responds to CPU 11 in place of the first and second DMA controllers when IO access to the prescribed IO address occurs. A bridge circuit 20 is constituted by adding the first DMA controller, an interrupting controller and a programmable interval timer. The bridge circuit 51 has almost the same configuration as the bridge circuit 20 at a PC side and also incorporates the second DMA controller for managing a DMA request and an interruption request which are generated on a secondary ISM bus 53 and an interruption controller.

公开(公告)号：JP2005308421A

公开(公告)日：2005-11-04

申请号：JP2004122204

申请日：2004-04-16

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： TANIGUCHI MASAYOSHI ,  YOKOTA TOSHIHIKO ,  MAJIMA ISAMU

IPC: G01R31/28 ,  G06F11/22

Abstract: PROBLEM TO BE SOLVED: To realize test methods in actual operation conditions (actual operation test, At speed test) for the LSSD (Lever-Sensitive Scan Design) scanning test. SOLUTION: A micro computer (ASIC) comprises a scan chain for the LSSD scanning test, and a clock generating circuit 10 which generates a shift clock which has each latch circuit of the scan chain latch a test pattern and a clock for performing the test which imports the output of an circuit to be tested corresponding to the test pattern, and supplies them to the scan chain. The clock generating circuit 10 generates at least a part of a shift clock by converting an external clock to a fast clock using a clock chopper 11. The shift clock is delayed by a multiplexer for delay 12 to generate the clock for performing the test. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：实现LSSD（杠杆敏感扫描设计）扫描测试的实际操作条件（实际操作测试，速度测试）中的测试方法。 解决方案：微计算机（ASIC）包括用于LSSD扫描测试的扫描链，以及时钟产生电路10，其生成具有扫描链的每个锁存电路锁存测试图案的移位时钟和用于执行的时钟 该测试根据测试图案输入要测试的电路的输出，并将其提供给扫描链。 时钟产生电路10通过使用时钟斩波器11将外部时钟转换为快速时钟来产生移位时钟的至少一部分。移位时钟由延迟器12的多路复用器延迟以产生用于执行测试的时钟。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2006172335A

公开(公告)日：2006-06-29

申请号：JP2004367038

申请日：2004-12-20

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： TANIGUCHI MASAYOSHI ,  MAJIMA ISAMU ,  USAMI ATSUSHI

IPC: G06F12/16 ,  G11C29/04 ,  H01L21/82

CPC classification number: G11C29/789

Abstract: PROBLEM TO BE SOLVED: To provide a SoC applied with a voltage island which can prevent being unable to perform memory access in other modules when a certain module is powered-on. SOLUTION: A microcomputer includes a plurality of memories with redundancies, a fuse cell 101, a shift register 10 and a controlling circuit 20. The fuse cell 101 stores configuration information for controlling switch of memory components in the plurality of memories. The shift register 10, placed corresponding to each memory, receives the configuration information toward the memories from the fuse cell 101 and hold it. The controlling circuit 20 controls operations of the shift register 10. The shift register 10 includes a shift part which receives data of the configuration information to transfer the data to the other shift register 10, and a latch part which holds the data input into the shift part. The controlling circuit 20 controls whether to hold the input data of the shift register 10 in the latch part. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种应用电压岛的SoC，当某个模块通电时，可以防止在其他模块中不能执行存储器访问。 解决方案：微计算机包括多个具有冗余的存储器，熔丝单元101，移位寄存器10和控制电路20.熔丝单元101存储用于控制多个存储器中的存储器组件的开关的配置信息。 对应于每个存储器放置的移位寄存器10从熔丝单元101向存储器接收配置信息并保持它。 控制电路20控制移位寄存器10的动作。移位寄存器10包括：移位部，其接收配置信息的数据，将数据传送给其他移位寄存器10;锁存部， 部分。 控制电路20控制是否将移位寄存器10的输入数据保持在锁存部分中。 版权所有（C）2006，JPO＆NCIPI