Abstract:
PROBLEM TO BE SOLVED: To surely prevent access to a memory protected area when an invasion into the inside of an SoC is made from the outside, and make the execution of debugging by a boundary scan test possible. SOLUTION: A microcomputer is provided with; a TAP controller 120 which monitors input to a processor 111 from the outside; an instruction decoder 131; inner registers 141 and 142 which monitor whether access destination addresses for the access by the processor 111 to a ROM 113 and an SRAM 114 exist in a preliminarily fixed protected area; comparators 143 and 144; inner registers 145 and 146 which are access control means; and multiplexers 147 and 149. When control instructions to the processor 111 are detected and also the access to the protected area from the processor 111 is detected, the access destination addresses are replaced with the addresses of the ROM 201 and SRAM 202 of an additional circuit block 200 prepared by a developer. COPYRIGHT: (C)2005,JPO&NCIPI
Abstract:
PROBLEM TO BE SOLVED: To debug by reading or rewriting contents of an arbitrary register in an SoC by an an LSSD scan test. SOLUTION: The SoC is provided with a scan chain in which a plurality of latch circuits are connected like a chain and which executes a scan test and a debug circuit 100 for designating the specific latch circuit configuring the scan chain for reading data while executing the scan test to the scan chain. The scan chain configures a feedback loop by returning the output to the input of the leading latch circuit. Also, there are a plurality of scan chains, and each scan chains is configured of the same number of latch circuits, and provided with the latch circuit for executing the scan test and the dummy latch circuit for arranging the number of the latch circuits configuring the scan chain. COPYRIGHT: (C)2005,JPO&NCIPI
Abstract:
PROBLEM TO BE SOLVED: To provide a system where DMA transfer is correctly executed even when DMA controllers exist in a self system and also in a docking station by adding the respective specified first and second DAM controllers and a control circuit. SOLUTION: This system includes a first and second DMA controllers where prescribed IO addresses are respectively assigned and the control circuit which responds to CPU 11 in place of the first and second DMA controllers when IO access to the prescribed IO address occurs. A bridge circuit 20 is constituted by adding the first DMA controller, an interrupting controller and a programmable interval timer. The bridge circuit 51 has almost the same configuration as the bridge circuit 20 at a PC side and also incorporates the second DMA controller for managing a DMA request and an interruption request which are generated on a secondary ISM bus 53 and an interruption controller.
Abstract:
PROBLEM TO BE SOLVED: To realize test methods in actual operation conditions (actual operation test, At speed test) for the LSSD (Lever-Sensitive Scan Design) scanning test. SOLUTION: A micro computer (ASIC) comprises a scan chain for the LSSD scanning test, and a clock generating circuit 10 which generates a shift clock which has each latch circuit of the scan chain latch a test pattern and a clock for performing the test which imports the output of an circuit to be tested corresponding to the test pattern, and supplies them to the scan chain. The clock generating circuit 10 generates at least a part of a shift clock by converting an external clock to a fast clock using a clock chopper 11. The shift clock is delayed by a multiplexer for delay 12 to generate the clock for performing the test. COPYRIGHT: (C)2006,JPO&NCIPI
Abstract:
PROBLEM TO BE SOLVED: To provide a SoC applied with a voltage island which can prevent being unable to perform memory access in other modules when a certain module is powered-on. SOLUTION: A microcomputer includes a plurality of memories with redundancies, a fuse cell 101, a shift register 10 and a controlling circuit 20. The fuse cell 101 stores configuration information for controlling switch of memory components in the plurality of memories. The shift register 10, placed corresponding to each memory, receives the configuration information toward the memories from the fuse cell 101 and hold it. The controlling circuit 20 controls operations of the shift register 10. The shift register 10 includes a shift part which receives data of the configuration information to transfer the data to the other shift register 10, and a latch part which holds the data input into the shift part. The controlling circuit 20 controls whether to hold the input data of the shift register 10 in the latch part. COPYRIGHT: (C)2006,JPO&NCIPI