公开(公告)号：DE3380434D1

公开(公告)日：1989-09-21

申请号：DE3380434

申请日：1983-05-19

Applicant: IBM

Inventor： LOVGREN JEFFREY LYNN ,  THOMAS GEORGE CLARK ,  TRNKA JOHN THOMAS

IPC: H03M1/82 ,  H03M1/00 ,  H03M1/66

公开(公告)号：DE3063649D1

公开(公告)日：1983-07-14

申请号：DE3063649

申请日：1980-03-20

Applicant: IBM

Inventor： MOEN DAVID NORMAN ,  THOMAS GEORGE CLARK

IPC: G01R31/3185 ,  G11C19/00 ,  H03K23/00 ,  H03K23/54 ,  H03K23/58 ,  G06F7/00

Abstract: Data processing apparatus constructed in shift register logic is provided in a simple manner with an optional pulse counting function by incorporating additional switching logic (64) into a linear shift register of sequential stages (SRL 0, 1, 2, 3) thereof, the additional logic (64) being responsive to a pulse input (C CLOCK), a count enable input and the current stage of the stages to force Grey code pattern shifting within separate groups (COUNTER SEG 1, 2) of sequentially adjacent stages and pulse advance between each sequentially adjacent pair of the groups at the termination of each Grey code pattern cycle in the leading group of the pair. Both the linear shift function and the counting function are provided with the worst case inter stage connection spanning no more than a group.