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公开(公告)号：DE3477284D1
公开(公告)日：1989-04-20
申请号：DE3477284
申请日：1984-06-25
Applicant: IBM
Inventor： THOMAS VINCENT PHILIP
Abstract: A linear output multiplier has two pairs of differentially connected multiplying transistors (T13, T14 and T15 T16). One value Vx to be multiplied is supplied to the differential inputs of differential amplifier 1 and converted to corresponding differential currents I1 and I2. These currents are supplied to semiconductor junctions which generate logarithmically distorted voltages representing the one value Vx which are applied to the control electrodes of the multiplying transistors. The second value Vy to be multiplied is supplied to the differential inputs of differential amplifier 2 and converted to corresponding differential currents I3 and I4. The outputs from amplifier 2 are connected respectively to the tail connections of the two differential pairs of multiplier transistors. The outputs of the multiplying transistors are cross-coupled to provide four quadrant multiplying functions. Zero signal offset errors due to device Vbe mismatch are corrected by injecting a current equal to the standing current of the differential amplifier 2 into the two outputs of the differential amplifier. This means that with zero differential input to the amplifier (Vy=0) no current flows through the multiplying transistors and the zero output condition is ensured. Furthermore, any residual errors for non-zero input signals are proportional to the applied input signal Vy. The injected currents are developed by an additional current source (T24, R24) and current mirror arrangement (T17, T18, T19, and T25).
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公开(公告)号：DE3483265D1
公开(公告)日：1990-10-25
申请号：DE3483265
申请日：1984-06-25
Applicant: IBM
IPC: G09G5/22 , G06F3/153 , G09G5/02 , G11C11/411 , G11C11/416 , H01L27/02
Abstract: Semiconductor integrated word organized store comprising a two-dimensional array of bistable storage cells linked by orthogonal word lines and pairs of bit lines. Each cell consists of two cross-coupled merged transistor logic (MTL) gates having a structure providing a vertical inverting base transistor and two complementary lateral injector transistors. A cell is driven by read/write logic pulses applied to the word lines and bit lines only. To read the contents of a word from the array, read logic drives the read injectors of the cells constituting the word at a high injector current level and the read injectors of all other cells at a low injector current level. To select a word for writing, the read logic drives the read injectors of the cells comprising the word at a low injector current level and all other cells at a high injector current level. The contents of the selected word may then be changed by differentially driving the cell write injectors over the bit lines. Output multiplexing of cells storing corresponding bit positions in the words is achieved simply by connecting the cell outputs together (dot ANDing). Logical output discrimination and interfacing is achieved by comparing the multiplexed output current with a threshold current. If the output current is less than the threshold current, the cell is storing a logical ONE. If the output current is greater than the threshold current, the cell is storing a logical ZERO.
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公开(公告)号：DE3373579D1
公开(公告)日：1987-10-15
申请号：DE3373579
申请日：1983-06-30
Applicant: IBM
Inventor： JONES JOHN WYN , THOMAS VINCENT PHILIP
Abstract: A cathode-ray tube controller uses a content addressable associative storage array (10) to generate repetitively a sequence of video control signals for a CRT to which it is attached. A binary coded counter (4) incremented by the system clock (CL) of the CRT provides a sequence of binary count values representing the running count of the CRT clock. This running count is continuously available and applied as an input search argument to the associative array. A plurality of predetermined count values, derived with reference to the running count, are stored as binary coded words in selected rows of the associative array. The match signals generated on the sense lines of the array as the running count value becomes equal to the predetermined count values in the array provide the video control signals to control the various display functions of the CRT. One of the signals is used to re-set the running count value so that the sequence of signals is repeated at regular intervals. The timing of the video control signals is determined solely by the running count values entered into store. An input data register (15) is provided in order to load words into the array to define or to change the functions of display. A read register (17) is provided in which interrogated words are read for test and event timing purposes.
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