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    2.
    发明专利
    未知

    公开(公告)号：DE1257460B

    公开(公告)日：1967-12-28

    申请号：DEJ0028981

    申请日：1965-09-11

    Applicant: IBM

    Inventor： THORPE ROBERT ALLEN

    IPC: G09G1/10 ,  H03M1/00

    Abstract: 1,081,517. Cathode-ray tube circuits; transistor circuits. INTERNATIONAL BUSINESS MACHINES CORPORATION. Sept. 1, 1965 [Sept. 17, 1964; Oct. 2, 1964; Jan. 15, 1965], No. 37319/65. Headings H3T and H4T. In an arrangement for deflecting the beam of a cathode-ray tube to trace Alpha-Numeric characters, vectors, &c., the deflection waveform comprises the ramp signal output of an integrator to which is supplied a first steady state signal, termed an overdrive signal, having an amplitude equal to a multiple of the deflection amplitude required, the integrator characteristic being such that, after a predetermined time interval, the amplitude of the ramp signal is equal to the required amplitude, a second steady state signal having the' latter amplitude being then supplied to the integrator. This arrangement results in an improvement in the linearity of the deflection over that which would result from charging the integrator only to the required amplitude. In one embodiment (Fig. 1) which is concerned with the X- deflection (a similar arrangement being employed for the Y-deflection) digital data representative of the absolute endpoint address of a vector is derived from a data processing unit (DPU) 21 and combined in adder 33 with digital signals from register 40 via gate 39 representative of the previous endpoint address X to derive the actual deflection required i.e. #X. The X and #X signals are then manipulated to produce the quantity X + 3#X (the overdrive signal) which is fed via register 40 to a digital-to-analogue decoder 65 producing a steady state signal as input to the integrator 67. At this instant the vector timer 75 unblanks the beam of the tube via control 77 for an interval T (all vectors, irrespective of length, are drawn in time T) during which the beam is deflected in accordance with the ramp signal generated by the integrator. In the interval T the circuitry generates the real endpoint address i.e. X + #X and at the end of the interval as determined by timer 75 supplies this signal to the integrator, the RC time constant of the latter being designed such that in time T the ramp signal will always travel onethird of the distance required to reach the X + 3#X level. The endpoint of the vectors so drawn X + #X now remains in the register as the initial point of the next vector. In a second embodiment (Fig. 2, not shown) the data-processing unit 21 supplies both the #X and the #X + X information thus allowing a simplification of the circuitry of Fig. 1 to be realized and in a further embodiment (Figs. 4 and 5, not shown) the digital-to-analogue comprises a plurality of resistors selectively swtiched into circuit.

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