公开(公告)号：JP2001222516A

公开(公告)日：2001-08-17

申请号：JP2001000007

申请日：2001-01-04

Applicant: IBM

Inventor： MICHAEL STEPHEN FLOYD ,  KEVIN F REIKKU ,  TIMOTHY M SUKAAGAN

IPC: G06F15/78 ,  G06F11/00 ,  G06F11/14 ,  G06F11/22 ,  G06F15/16

Abstract: PROBLEM TO BE SOLVED: To provide a method and a system for decreasing complexity related to the test and utilization of a multicore central processing unit(CPU). SOLUTION: A data processing system 100 is provided with at least one CPU 110 provided with first and second processing cores 160A and 160B at least. Besides, the data processing system 100 is provided with input devices 162A and 162B for receiving control input for specifying which processing core is to be used. Further, the data processing system 100 is provided with a configuration logic for comprising the data processing system by making at least one processing core active and making all or at least one processing core inactive corresponding to the control input in response to the reception of the control input.

公开(公告)号：JPH10301846A

公开(公告)日：1998-11-13

申请号：JP9758998

申请日：1998-04-09

Applicant: IBM

Inventor： RAVI KUMAR ARIMIRI ,  JOHN STEPHEN DODDSON ,  JERRY DON LEWIS ,  TIMOTHY M SUKAAGAN

IPC: G06F12/16 ,  G06F11/00 ,  G06F12/08

Abstract: PROBLEM TO BE SOLVED: To bypass a defect inside a cache used by the processor of a computer system by using a restoration mask, preventing a defective cache line from becoming a cache hit and preventing the defective cache line from being selected as a sacrifice for cache replacement. SOLUTION: This system is provided with the restoration mask 76 provided with the array of bit fields each one of which corresponds to each one of plural cache lines inside the cache. A specified cache line inside the cache is identified as the defective one. The corresponding bit field inside the array of the restoration mask 76 is set and it is indicated that the defect is present in the defective cache line. Based on the corresponding bit field inside the array of the restoration mask 76, access to the defective cache line is prevented. By executing the steps, the defect inside the cache is bypassed.