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    SIGNAL DELAY CIRCUIT
    2.
    发明专利
    SIGNAL DELAY CIRCUIT 失效

    公开(公告)号：JPH01206722A

    公开(公告)日：1989-08-18

    申请号：JP31867388

    申请日：1988-12-19

    Applicant: IBM

    Inventor： ARUBAATO MANHI CHIYU ,  UIRIAMU ROBAATO GURIFUIN

    IPC: H03H11/26 ,  H01L27/092 ,  H03K5/00 ,  H03K5/13

    Abstract: PURPOSE: To reduce a surface area and a power consumption by arraying a 1st circuit which has a 1st and a 2nd series-connected FET and a 2nd circuit which has a 3rd FET in parallel to each other, and connecting them between an input and an output terminal. CONSTITUTION: When the voltage at the input terminal IN is 0V, voltages nodes(Nd) A-C and the terminal OUT are 5V and when the voltage IN begins to rise at time t1 and reaches Vdd/2 as the proximity switch point of an inverting circuit 26 at time t1 , the voltage of NdA begins to fall. When the voltages of the control electrodes of N.FETs 18 and 20 rise while the voltage of NdA falls, an FET 18 turns on and then the voltage of NdB falls, so that the voltages at the terminals OUT and NdC fall. The voltage at the terminal OUT falls to Vdd/2 at time t2 and the delay from the terminal IN to the terminal OUT becomes equal to t2 -t1 . Then the voltage at the terminal OUT falls to 0V at time t3 . The voltage IN begins to fall at time t4 , reaches Vdd/2 at time t4 , and then begins to rise thereafter. At time t6 , the voltage at the terminal OUT reaches Vdd/2 and at time t7 , a source voltage Vdd corresponding to the full power is obtained.

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