1.
    发明专利
    未知

    公开(公告)号:DE69027515T2

    公开(公告)日:1997-01-23

    申请号:DE69027515

    申请日:1990-12-07

    Applicant: IBM

    Abstract: A data processing system includES an arrangement for modifying the usual priority arbitration of an input/output channel controller (IOCC) used in granting direct memory access (DMA) service among contending peripheral devices sharing a common peripheral bus. The IOCC includes logic for conditioning the established priority arbitration scheme based upon the data status of the data buffers. If the higher priority requesting device requires a data transfer between the system memory and the IOCC prior to performing an operation directly between the IOCC and the peripheral device, the priority will instead be granted to a lower priority peripheral device that does not require a system memory access operation.

    Apparatus for conditioning priority arbitration in buffered direct memory addressing

    公开(公告)号:HK203096A

    公开(公告)日:1996-11-15

    申请号:HK203096

    申请日:1996-11-07

    Applicant: IBM

    Abstract: A data processing system includES an arrangement for modifying the usual priority arbitration of an input/output channel controller (IOCC) used in granting direct memory access (DMA) service among contending peripheral devices sharing a common peripheral bus. The IOCC includes logic for conditioning the established priority arbitration scheme based upon the data status of the data buffers. If the higher priority requesting device requires a data transfer between the system memory and the IOCC prior to performing an operation directly between the IOCC and the peripheral device, the priority will instead be granted to a lower priority peripheral device that does not require a system memory access operation.

    Apparatus for conditioning priority arbitration in buffered direct memory addressing

    公开(公告)号:SG43719A1

    公开(公告)日:1997-11-14

    申请号:SG1996000147

    申请日:1990-12-07

    Applicant: IBM

    Abstract: A data processing system includES an arrangement for modifying the usual priority arbitration of an input/output channel controller (IOCC) used in granting direct memory access (DMA) service among contending peripheral devices sharing a common peripheral bus. The IOCC includes logic for conditioning the established priority arbitration scheme based upon the data status of the data buffers. If the higher priority requesting device requires a data transfer between the system memory and the IOCC prior to performing an operation directly between the IOCC and the peripheral device, the priority will instead be granted to a lower priority peripheral device that does not require a system memory access operation.

    5.
    发明专利
    未知

    公开(公告)号:DE69027515D1

    公开(公告)日:1996-07-25

    申请号:DE69027515

    申请日:1990-12-07

    Applicant: IBM

    Abstract: A data processing system includES an arrangement for modifying the usual priority arbitration of an input/output channel controller (IOCC) used in granting direct memory access (DMA) service among contending peripheral devices sharing a common peripheral bus. The IOCC includes logic for conditioning the established priority arbitration scheme based upon the data status of the data buffers. If the higher priority requesting device requires a data transfer between the system memory and the IOCC prior to performing an operation directly between the IOCC and the peripheral device, the priority will instead be granted to a lower priority peripheral device that does not require a system memory access operation.

    APPARATUS FOR CONDITIONING PRIORITY ARBITRATION

    公开(公告)号:AU6661090A

    公开(公告)日:1991-06-20

    申请号:AU6661090

    申请日:1990-11-15

    Applicant: IBM

    Abstract: A data processing system includES an arrangement for modifying the usual priority arbitration of an input/output channel controller (IOCC) used in granting direct memory access (DMA) service among contending peripheral devices sharing a common peripheral bus. The IOCC includes logic for conditioning the established priority arbitration scheme based upon the data status of the data buffers. If the higher priority requesting device requires a data transfer between the system memory and the IOCC prior to performing an operation directly between the IOCC and the peripheral device, the priority will instead be granted to a lower priority peripheral device that does not require a system memory access operation.

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