Random binary data signal frequency and phase compensation circuit
    1.
    发明授权
    Random binary data signal frequency and phase compensation circuit 失效
    随机二进制数据信号频率和相位补偿电路

    公开(公告)号:US3701039A

    公开(公告)日:1972-10-24

    申请号:US3701039D

    申请日:1968-10-28

    Applicant: IBM

    CPC classification number: H03L7/0891 H03D13/004

    Abstract: A phase lock oscillator includes a phase discriminator that develops an error signal by comparing a clock from a voltage controlled oscillator with incoming random data bits. In the absence of data, the phase lock oscillator is inactive. However, when data is sensed, a logic and delay network in the phase discriminator develops an error voltage of suitable polarity and amplitude, indicative of the lead or lag between the data and clock signals. The error voltage is applied to the voltage controlled oscillator to modify the frequency and phase of the clock. Furthermore, first and second integrations are provided by the phase discriminator and an integrator respectively so that the steady state phase error is held close to zero.

    Abstract translation: 锁相振荡器包括通过将来自压控振荡器的时钟与输入随机数据比进行比较来产生误差信号的相位鉴别器。 在没有数据的情况下,锁相振荡器不起作用。 然而,当检测到数据时,鉴相器中的逻辑和延迟网络产生合适的极性和幅度的误差电压,指示数据和时钟信号之间的引导或滞后。 误差电压被施加到压控振荡器以修改时钟的频率和相位。 此外,第一和第二积分分别由相位鉴别器和积分器提供,使得稳态相位误差保持接近于零。

    PSK MODULATION IN AC BIAS DATA RECORDING

    公开(公告)号:CA1180442A

    公开(公告)日:1985-01-02

    申请号:CA414991

    申请日:1982-11-05

    Applicant: IBM

    Abstract: PSK MODULATION IN AC BIAS DATA RECORDING In a data recording system employing an AC bias signal that is superimposed on the data signal, the AC bias signal is phase modulated to compensate for the difference in the phase angle between the alternating bias and the data signals. The frequency of the AC bias signal is no greater than ten times the frequency of the data signal.

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