Abstract:
A phase lock oscillator includes a phase discriminator that develops an error signal by comparing a clock from a voltage controlled oscillator with incoming random data bits. In the absence of data, the phase lock oscillator is inactive. However, when data is sensed, a logic and delay network in the phase discriminator develops an error voltage of suitable polarity and amplitude, indicative of the lead or lag between the data and clock signals. The error voltage is applied to the voltage controlled oscillator to modify the frequency and phase of the clock. Furthermore, first and second integrations are provided by the phase discriminator and an integrator respectively so that the steady state phase error is held close to zero.
Abstract:
PSK MODULATION IN AC BIAS DATA RECORDING In a data recording system employing an AC bias signal that is superimposed on the data signal, the AC bias signal is phase modulated to compensate for the difference in the phase angle between the alternating bias and the data signals. The frequency of the AC bias signal is no greater than ten times the frequency of the data signal.