公开(公告)号：DE1499722B1

公开(公告)日：1972-05-25

申请号：DE1499722

申请日：1966-10-11

Applicant: IBM DEUTSCHLAND

Inventor： HOWARD OTTAWAY GERALD ,  PAINKE HELMUT ,  RAGLAND THOMAS ,  SCHELER TITUS ,  WILL HELMUT ,  VAUGHN WRIGHT WILLIAM

IPC: G06F9/26 ,  G06F9/20

Abstract: 1,107,486. Microprogramming. INTERNATIONAL BUSINESS MACHINES CORPORATION. 25 Aug., 1966 [22 Oct., 1965], No. 38140/66. Heading G4A. Bits from a stored word are subjected to a variable logical operation to get the address of the next word. An address applied to a computer microprogramme read-only store controls three decoders. The first two decoders select a word location in the store and the third decoder selects and passes to a register one of three portions of the word as the next micro-instruction. Either of two of the portions fills the register but the third leaves a part of the register unchanged. The next store address is obtained from sections of said register, said " part " of the register feeding the second decoder, another part feeding the third decoder, and a third part being applied to the first decoder via a " use " circuit which either passes the third part unchanged, or AND's or OR's or EXCL-OR's the bits of the third part with corresponding bits from one of a number of working registers in the computer. What the " use " circuit does to the third part is controlled by other bits from the current microinstruction.

公开(公告)号：DE1499215A1

公开(公告)日：1970-07-23

申请号：DE1499215

申请日：1965-06-28

Applicant: IBM

Inventor： ANNE BLAAUW GERRIT ,  VAUGHN WRIGHT WILLIAM ,  HALL LARSON RUSSELL

IPC: G06F9/28 ,  G06F9/48 ,  G06F9/00

Abstract: 1,076,775. Data processors. INTERNATIONAL BUSINESS MACHINES CORPORATION. June 16, 1965 [June 30, 1964], No. 25360/65. Heading G4A. In a data processor, selection means permit one of a plurality of independently-operable sources of control signal patterns to present its signal patterns to control data manipulation, in accordance with a priority ranking. The sources are seven so called " request rings ", respectively relating to the following aspects of operations in order of decreasing priority: (1) input output, (2) data transfer, (3)-(5) operand control, (6) instruction load, (7) byte processing. The priority order may be departed from in that " instruction load " may be given priority over " operand control " when necessary. The operating cycle has an early B (bus) time and a late R (register) time, and each request ring has corresponding B and R latches. The B latches control the R latches and the R latches, via logic, control the B latches, the logic being also responsive to the current programmed instruction and machine conditions. A three-address programmed instruction activates the required rings which produce outputs specifying their identity and control signals. A priority unit responds to these identities to cause an " early decoder " corresponding to the highest priority requesting ring to decode the ring output. The decoded output is applied to gates and a gate control register both directly to control the B portion of the cycle and via an encoder, further B and R latches (to provide a delay) and a " late decoder" to control the R portion. The gates control transfer of data between memory and processing elements in the processor. The output of the selected early decoder also advances the associated ring to its next state (which depends on present state, instruction and machine conditions). The R portion of one cycle may overlap the B portion of the next except when the two portions require use of common data paths. The latter condition is detected by job conflict logic receiving the input to the late decoder, and results in the priority unit holding up the second cycle but not enabling the early decoder. Delays can be provided at the outputs of the early and late decoders to split cycles again. A cycle may have one of two lengths by controlling the lengths of the B and R pulses. Four main buses link the multi-byte MDR (memory data register) with other registers etc. A register is provided for saving operation code bits during indirect addressing. Error checking.-Parity checks are performed at the common input to the job conflict logic and the late decoder, and also at the output of the latter. Two of the four main buses are parity checked and since each operation involving use of the buses uses all four (zeroes being forced where necessary) this parity checking also in effect checks the control circuitry Invalid addresses and operation codes, and accessing by a programme of a memory address greater than a limit specified for the programme are detected. Error detection results in storing of register contents for diagnosis purposes (no details).

公开(公告)号：DE1499727A1

公开(公告)日：1972-04-13

申请号：DE1499727

申请日：1966-10-12

Applicant: IBM DEUTSCHLAND INTERNAT BUERO

Inventor： HOWARD OTTAWAY GERALS ,  PAINKE HELMUT ,  SCHELER TITUS ,  WILL HELMUT ,  VAUGHN WRIGHT WILLIAM

IPC: G06F9/26 ,  G06F9/00

Abstract: 1,105,394. Data storage: micro-programme control arrangements. INTERNATIONAL BUSINESS MACHINES CORPORATION. 31 Aug., 1966 [22 Oct., 1965], No. 38738/66. Heading G4A. Certain of the data in a storage register associated with a digital electric data store can be maintained from one storage access cycle to another, means being provided responsive to the state of certain other data positions to select which bytes of a next-to-be addressed word in the store are to be moved into the storage register. In digital electric data-storage apparatus wherein each storage word includes as a portion thereof at least a portion of the address of the next succeeding storage word, storage space is saved due to the fact that when dealing with a sequence of storage words located within adjacent areas of the store the common high order address bits are saved from one storage access cycle to the next. The invention has particular application to micro-programme control using read-only stores. In the arrangement shown (Fig. 1), a read only store (ROS) 22 stores 60-bit storage words which are divided into three instruction words A, B, C of 16, 22 and 22 bits each respectively. One only of these words A, B, or C is transferred during any storage access cycle into ROS register 24 the particular one chosen depending on the configuration of bits 16 and 17 in ROS address register (ROSAR) 28, these bits, originating from the previous micro-instruction, being decoded by word select decoder WD SEL DEC 26 (shown in detail in Fig. 2, not shown). In those cases where word A is selected, bits 10 to 15 of ROS REG 24 remain undisturbed to form the high order part of the next address. USE circuit 34 allows optional (programmed) modification of address bits 18-21 of ROS REG 24 before these bits are applied to ROSAR 29. Bits 1-9, forming the order part of the instruction word, are applied to decode circuits 38 in conventional manner. ROS REG 24 is shown in more detail in Fig. 2 (not shown).