公开(公告)号：GB2316204A

公开(公告)日：1998-02-18

申请号：GB9715399

申请日：1997-07-23

Applicant: IBM

Inventor： HERGER LORRAINE MARIA PAOLA ,  MAK KWON-KEN ,  OCHELTREE KENNETH BLAIR ,  TSAI TU-CHIH ,  WAZLOWSKI MICHAEL EDWARD

IPC: G06F12/08

Abstract: Multiple processors 13-1 - 13-8 with associated caches 14-1 - 15-8 are connected through a plurality of interconnects 1-1 - 1-3, typically arranged in a hierarchical tree, to a shared memory 9. Each interconnect has multiple Local ports 3 that connect either to processors or to other interconnects, and a Global port 4 connected to a Local port of another interconnect, and a directory 11 in each interconnect has a routing record, for each line of storage in the system memory, having an entry for each port to indicate whether a copy of the line is being held by a processor or memory reached through that port. Information is shared in caches in the system using these path indicators in the directories, and, when a processor acquires a copy of information exclusively, it uses the path indicators to invalidate all the other cached copies so that it can write to an exclusive copy.