公开(公告)号：GB2520942A

公开(公告)日：2015-06-10

申请号：GB201321307

申请日：2013-12-03

Applicant: IBM

Inventor： JACOBI CHRISTIAN ,  PFLANZ MATTHIAS ,  WEBBER KAI ,  SCHUH STEFAN ,  DITTRICH JENS

IPC: G06F12/08 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0862 ,  G06F12/0882

Abstract: Disclosed is a multi-processor system 1 with a multi-level cache L1, L2, L3, L4 structure between the processors 10, 20, 30 and the main memory 60. The memories of at least one of the cache levels is shared between the processors. A page mover 50 is positioned closer to the main memory and is connected to the cache memories of the shared cache level, to the main memory and to the processors. In response to a request from a processor the page mover fetches data of a storage area line-wise from one of the shared cache memories or the main memory, while maintaining cache memory access coherency. The page mover has a data processing engine that performs aggregation and filtering of the fetched data. The page mover moves processed data to the cache memories, the main memory or the requesting processor. The data processing engine may have a filter engine that filters data by comparing all elements of a fetched line from a source address of a fetched line from a source address of the shared cache level or main memory with filter arguments to create a bitmask buffer of the target storage area.