公开(公告)号：DE3872737D1

公开(公告)日：1992-08-20

申请号：DE3872737

申请日：1988-01-22

Applicant: IBM

Inventor： GOULD ELLIOT L ,  KEMERER DOUGLAS W ,  PIRO RONALD A ,  RICHARDSON GUY R ,  WELLBURN DEBORAH A ,  MCALLISTER LANCE A

IPC: H01L21/82 ,  H01L21/822 ,  H01L27/02 ,  H01L27/04 ,  H01L27/118

公开(公告)号：DE3872737T2

公开(公告)日：1993-03-04

申请号：DE3872737

申请日：1988-01-22

Applicant: IBM

Inventor： GOULD ELLIOT L ,  KEMERER DOUGLAS W ,  PIRO RONALD A ,  RICHARDSON GUY R ,  WELLBURN DEBORAH A ,  MCALLISTER LANCE A

IPC: H01L21/82 ,  H01L21/822 ,  H01L27/02 ,  H01L27/04 ,  H01L27/118

公开(公告)号：CA1290076C

公开(公告)日：1991-10-01

申请号：CA556670

申请日：1988-01-15

Applicant: IBM

Inventor： GOULD ELLIOT L ,  KEMERER DOUGLAS W ,  MCALLISTER LANCE A ,  PIRO RONALD A ,  RICHARDSON GUY R ,  WELLBURN DEBORAH A

IPC: H01L21/82 ,  H01L21/822 ,  H01L27/02 ,  H01L27/04 ,  H01L27/118

Abstract: A Method Of Combining Gate Array and Standard Cell Circuits On A Common Semiconductor Chip A method and semiconductor structure are provided for intermixing circuits of two or more different cell classes, such as standard cells and gate array cells, on a common chip or substrate with minimum gound rule separation between adjacent cells of different classes. Cell locations are defined with given boundaries and contiguously arranged on the surface of a semiconductor chip, and then either standard cell type or gate array type circuits are formed within any of the cell locations to provide a structure for balancing chip density and performance versus hardware turn-around-time. BU9-87-002