公开(公告)号：JPH10189889A

公开(公告)日：1998-07-21

申请号：JP33006097

申请日：1997-12-01

Applicant: IBM

Inventor： WIN KIN RAKU ,  WEI WAN

IPC: G11C11/407 ,  G11C5/02 ,  G11C5/14 ,  G11C11/401 ,  H01L27/10

Abstract: PROBLEM TO BE SOLVED: To provide specifications in which a DRAM macro and a logic core are arranged on a same chip. SOLUTION: A chip comprises multi-bank SDRAM(synchronous DRAM) macros located at its upper part and lower part, and a logic core is positioned between the upper and lower SDRAM macro. A PLL 41 is placed on the one side of the center of the chip, and clocks from the PLL 41 are guided to the center of the chip and buffered to drive the SDRAM macros and the logic core.