公开(公告)号：JP2012104104A

公开(公告)日：2012-05-31

申请号：JP2011217087

申请日：2011-09-30

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： NEIL ANTHONY CAMPBELL ,  NORTH GERAINT ,  WOODWARD GRAHAM

IPC: G06F9/455 ,  G06F12/14

CPC classification number: G06F12/1009 ,  G06F8/52

Abstract: PROBLEM TO BE SOLVED: To provide a dynamic binary translator apparatus for translating a first block of one page size into a second block of another page size.SOLUTION: An apparatus includes a redirection page mapper 514 responsive to a memory page characteristic of a first memory 506 for mapping an address of the first memory to an address of a second memory 512, a memory fault behavior detector 516 operable to detect memory fault during execution of a second block and to accumulate a fault count to a trigger threshold, and a regeneration component 518 responsive to the fault count reaching the trigger threshold to discard the second block and cause a first block to be retranslated into a retranslated block with its memory references remapped by a page table walk.

Abstract translation: 要解决的问题：提供一种用于将一页大小的第一块翻译成另一页大小的第二块的动态二进制翻译器装置。 解决方案：一种装置包括响应于第一存储器506的存储器页特性的重定向页映象器514，用于将第一存储器的地址映射到第二存储器512的地址;存储器故障行为检测器516，其可操作以检测 在第二块的执行期间存储器故障并且将故障计数累积到触发阈值;响应于故障计数达到触发阈值的再生组件518，以丢弃第二块并使得第一块被重新翻译成重新传输的块 其内存引用由页表步进重新映射。 版权所有（C）2012，JPO＆INPIT

公开(公告)号：CA2756041A1

公开(公告)日：2012-05-10

申请号：CA2756041

申请日：2011-10-21

Applicant: IBM

Inventor： CAMPBELL NEIL A ,  NORTH GERAINT ,  WOODWARD GRAHAM

IPC: G06F8/52 ,  G06F12/00

Abstract: A dynamic binary translator apparatus, method and program for translating a first block of binary computer code intended for execution in a subject execution environment having a first memory of one page size into a second block for execution in a second execution environment having a second memory of another page size, comprising a redirection page mapper responsive to a page characteristic of the first memory for mapping an address of the first memory to an address of the second memory; a memory fault behaviour detector operable to detect memory faulting during execution of the second block and to accumulate a fault count to a trigger threshold; and a regeneration component responsive to the fault count reaching the trigger threshold to discard the second block and cause the first block to be retranslated with its memory references remapped by a page table walk.

公开(公告)号：CA2756041C

公开(公告)日：2019-02-19

申请号：CA2756041

申请日：2011-10-21

Applicant: IBM

Inventor： CAMPBELL NEIL A ,  NORTH GERAINT ,  WOODWARD GRAHAM

IPC: G06F8/52 ,  G06F12/00

Abstract: A dynamic binary translator apparatus, method and program for translating a first block of binary computer code intended for execution in a subject execution environment having a first memory of one page size into a second block for execution in a second execution environment having a second memory of another page size, comprising a redirection page mapper responsive to a page characteristic of the first memory for mapping an address of the first memory to an address of the second memory; a memory fault behaviour detector operable to detect memory faulting during execution of the second block and to accumulate a fault count to a trigger threshold; and a regeneration component responsive to the fault count reaching the trigger threshold to discard the second block and cause the first block to be retranslated with its memory references remapped by a page table walk.