公开(公告)号：JP2007287143A

公开(公告)日：2007-11-01

申请号：JP2007099321

申请日：2007-04-05

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： MCBRIDE CHAD B ,  IRISH JOHN D ,  WOTTRENG ANDREW H

IPC: G06F12/10

CPC classification number: G06F12/1081 ,  G06F12/1027

Abstract: PROBLEM TO BE SOLVED: To provide an improved technology which processes an I/O address conversion cache error caused by an I/O command in a CPU. SOLUTION: A CPU hardware can buffer the I/O command that has caused the I/O address conversion cache error in a command queue until an I/O address conversion cache is updated by using required information. When the I/O address conversion cache is updated, the CPU reissues the I/O command from the command queue, converts an address of the I/O command at convenient time, and executes and processes the command as if the cache miss has not occurred. Thus, an I/O device does not need to process an error response from the CPU, the I/O command is processed by the CPU, and the I/O command is not canceled. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供一种处理由CPU中的I / O命令引起的I / O地址转换高速缓存错误的改进技术。 解决方案：CPU硬件可以缓冲I / O命令，导致命令队列中的I / O地址转换高速缓存错误，直到通过使用所需信息更新I / O地址转换缓存。 当I / O地址转换缓存更新时，CPU从命令队列中重新发出I / O命令，在方便的时间转换I / O命令的地址，并执行并处理命令，就好像高速缓存未命中一样 发生。 因此，I / O设备不需要处理来自CPU的错误响应，I / O命令由CPU处理，I / O命令不会被取消。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2007048296A

公开(公告)日：2007-02-22

申请号：JP2006217586

申请日：2006-08-09

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： WOTTRENG ANDREW H ,  MCBRIDE CHAD B

IPC: G06F12/10 ,  G06F3/06 ,  G06F12/08

CPC classification number: G06F12/0891

Abstract: PROBLEM TO BE SOLVED: To provide a first method for removing entries from an address cache, in a first aspect.
SOLUTION: This first method includes steps of (1) writing data to a register; and (2) removing a plurality of address cache entries from the address cache based on the data written to the register.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：在第一方面中，提供从地址缓存中移除条目的第一方法。 解决方案：该第一种方法包括以下步骤：（1）将数据写入寄存器; 和（2）基于写入寄存器的数据从地址高速缓存中移除多个地址高速缓存条目。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：CA1158780A

公开(公告)日：1983-12-13

申请号：CA377206

申请日：1981-05-08

Applicant: IBM

Inventor： BODNER RONALD E ,  CROOKS THOMAS L ,  WOTTRENG ANDREW H

IPC: G06F13/00

Abstract: STORAGE ADDRESSING CONTROL APPARATUS Addressing control apparatus is structured to provide either byte or word addressing of storage organized on a word basis. The storage address register is made shiftable whereby for byte operations it is shifted, and the bit shifted out of the register is used for byte selection. The contents of the storage address register are used to address storage for both word and byte addressing, and no change is required. The storage access, however, for byte addressing takes place after the shift is completed and the timing is adjusted to account for the shift operation. Gate control logic is modified to facilitate the byte selection. RO980-003