公开(公告)号：US3780312A

公开(公告)日：1973-12-18

申请号：US3780312D

申请日：1971-12-30

Applicant: IBM

Inventor： LIN Y ,  YAO Y

IPC: H03K19/168 ,  G11C11/14

CPC classification number: H03K19/168

Abstract: A threshold logic device is provided using magnetic bubble domains. The presence and absence of bubble domains are the logic inputs to the device and the logic gate itself is comprised of a plurality of series connected sensing elements. Magnetoresistive sensing devices are particularly suitable. Each sensing element is given a particular geometry or thickness in order to achieve weighting of the logic inputs. The threshold of the device is internal in an associated detector and can be varied by changing the measuring current through the sensing elements in the case of magnetoresistive sensing elements. Depending on the sum of the weighted inputs being at least equal to the threshold value, or less than this value, the binary output of the device will be one or zero, respectively.

Abstract translation: 使用磁性气泡域提供阈值逻辑器件。 气泡区域的存在和不存在是器件的逻辑输入，逻辑门本身由多个串联连接的感测元件组成。 磁阻感测装置是特别合适的。 给每个传感元件一个特定的几何形状或厚度，以实现逻辑输入的加权。 器件的阈值在相关的检测器内部，并且可以通过在磁阻感测元件的情况下改变通过感测元件的测量电流来改变。 根据加权输入的总和至少等于阈值或小于该值，设备的二进制输出将分别为1或0。

公开(公告)号：US3760381A

公开(公告)日：1973-09-18

申请号：US3760381D

申请日：1972-06-30

Applicant: IBM

Inventor： YAO Y

IPC: G11C11/419 ,  G11C7/02 ,  G11C11/404 ,  G11C11/409 ,  G11C11/4091 ,  G11C11/4099 ,  G11C11/24 ,  G11C7/06

CPC classification number: G11C11/4099 ,  G11C11/404 ,  G11C11/4091

Abstract: A sensing circuit which is responsive to binary information represented by the level of charge in a capacitor is disclosed. The circuit comprises a differential amplifier; the nodes of which are connected to bucket brigade sense amplifier arrangements which are in turn connected to bit lines to which a plurality of memory device which store information in the form of charge are connected. Each bit line portion connected to the bucket brigade sense amplifier represents half of a bit line to which a plurality of storage devices (such as a capacitor in series with an FET gate) are connected. Each half of the bit line is also connected to a reference capacitor via an actuable FET device or other stored charge memory device. Each of the bucket brigade sense amplifiers consists of an output capacitance which is connected in parallel with the bit line capacitances of each half of the bit line via an actuable FET device. A source of voltage for charging the bit line capacitances is connected to the bit line halves via an actuable FET device and is utilized to charge the bit line capacitance, the output capacitance and a reference capacitor of one of the bit line halves. In operation, both bit line halves are charged to some voltage which is usually equal to the voltage to which the capacitance of a selected memory cell can be charged. At the same time, a reference capacitor is charged to approximately one half the voltage to which the selected cell capacitance can be charged. If the reference capacitor is to be charged to half the voltage of a storage cell, the size of the reference capacitor should be equal to that of the storage capacitor. Another way of implementing the reference capacitor is to use a reference capacitor half the size of a storage capacitor and discharge it completely each time before selecting a memory cell. If the memory cell capacitor is charged to full voltage (representing a binary ''''1'''') when the word line of the memory cell is activated for reading, no charge will flow from the bit line capacitance to the memory cell capacitance because both are at the same level. If the memory cell capacitance were empty (representing a binary ''''0'''') charge would flow from the bit line capacitance when reading occurred, filling the memory capacitor and reducing the bit line capacitor voltage by a small ion. When the bucket brigade circuit is actuated, no charge transfer occurs where the memory capacitor was full and a voltage approximately equal to the bit line charging voltage appears on one node of the differential amplifier. Where the memory capacitor was initially empty, charge transfer occurs to refill the bit line capacitance to its original level thereby depleting the output capacitance of charge and causing zero potential to be applied to one node of the differential amplifier. Simultaneously, with the appearance of the bit line charging voltage or zero at one node of the differential amplifier, a voltage equal to approximately half the bit line charging voltage appears at the other node of the differential amplifier. This results from the charging of the reference capacitance to one half the charging voltage. When reading of the reference capacitance occurs, charge from the bit line capacitance charges the reference capacitor up to its full value, depleting the bit line capacItance of an amount of charge equal to half the charge depleted from the opposite bit line capacitance when a memory cell storing a ''''0'''' is selected. When the bucket brigade sense amplifier is actuated, charge from the output capacitance thereof replenishes the bit line capacitance and leaves the output capacitance at a value of voltage approximately equal to one half of the charging voltage. In this manner, when a selected memory device associated with one half of a bit line is being read, the reference capacitance associated with the other half of the bit line is utilized to provide a voltage which is always the same regardless of the voltage on the selected device. The appropriate reference capacitor is selected by arranging the decoding such that when a memory device on one bit line half is selected, the reference capacitor on the other bit line half is always selected.

Abstract translation: 公开了一种响应由电容器中的电荷电平表示的二进制信息的感测电路。 电路包括差分放大器; 它们的节点被连接到桶旅读出放大器装置，这些装置又连接到以电荷形式存储信息的多个存储装置连接到的位线。 每个位线部分连接到降压

公开(公告)号：US3708688A

公开(公告)日：1973-01-02

申请号：US3708688D

申请日：1971-06-15

Applicant: IBM

Inventor： YAO Y

IPC: H03K5/003 ,  H03K19/096 ,  H03K19/08

CPC classification number: H03K19/096 ,  H03K5/003

Abstract: A number of field effect transistor circuits for driving loads having large capacitances is disclosed. Where insulated gate field effect transistors having relatively large driving current requirements are utilized, the interelectrode capacitances present are of such magnitude that, when the output circuit is energized from clocked sources normally OFF devices are turned ON providing spurious outputs. Circuit arrangements are provided for maintaining normally OFF devices in that condition during a portion of a given clock cycle by clamping an electrode (the gate of an FET) to a desired value while simultaneously isolating the clamped device or devices from changing potentials which may result from premature changes at the input of the circuit or elsewhere in the circuit. An inverter driver and an interface circuit for dynamic to static logic are shown.

Abstract translation: 公开了用于驱动具有大电容的负载的多个场效应晶体管电路。 在利用具有相对较大驱动电流要求的绝缘栅场效应晶体管的情况下，存在的电极间电容具有这样的大小，使得当输出电路从时钟源通电时，器件被接通，提供杂散输出。 提供电路布置用于在给定时钟周期的一部分期间通过将电极（FET的栅极）钳位到期望值来在该状态下维持正常OFF器件，同时将钳位的器件或器件从可能由 在电路输入或电路其他地方的过早变化。 示出了用于动态到静态逻辑的逆变器驱动器和接口电路。