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Patent Agency Ranking
公开(公告)号：CH620805A5
公开(公告)日：1980-12-15
申请号：CH534177
申请日：1977-04-29
Applicant: IBM
Inventor： YAO YING LUH
Abstract: A data bus is a common interconnection which serves as a two-way data link between inputs and outputs of several logic blocks in a time shared manner. A data bus arrangement is disclosed which can be utilized to interconnect a plurality of ports with each other and which utilize Josephson junction devices. Each of a plurality of ports represents the output from a computer or other logic circuit and these outputs represent inputs on control lines associated with each Josephson device which switch it. Each Josephson device is separately energized from its own current source and, upon switching, diverts current down a transmission line which has an impedance, Zo. In a single wire-over ground plane embodiment, all of the transmission lines are connected to a single node in a star arrangement. A terminating resistor which terminates each of the lines in a value of resistance equal to Zo is disposed in series in the transmission line and is intended to absorb signals coming from any port so there is no reflection of incoming signals back along the transmission line. From the node at which all the transmission lines are connected, a signal generated at one port, for example, passes in parallel to each of the other ports. There, depending on whether or not a sensing Josephson junction which is associated with each transmission line is enabled, the signal is sensed at a selected sensing junction. The present approach utilizes the fact that, when an input junction is in the unactuated state, it represents a short circuit presenting no internal impedance to the incoming current which can then be absorbed in a resistance which, in spite of the presence of the switchable device, remains as a termination equal in resistance to the characteristic impedance of the transmission line. A double wire over ground plane or a wire above and below ground plane embodiment is also shown, wherein the two wires or transmission lines associated with each input port are connected to a pair of nodes. Each line has the same characteristic impedance and each is terminated by a resistance equal to the characteristic impedance. In this arrangement, the resulting signal strength available for sensing can be two times the strength of the single wire embodiment, due to a reversal of the transmission line in the neighborhood of a sense gate.
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公开(公告)号：DE2704839A1
公开(公告)日：1978-01-05
申请号：DE2704839
申请日：1977-02-05
Applicant: IBM
Inventor： YAO YING LUH
Abstract: A data bus is a common interconnection which serves as a two-way data link between inputs and outputs of several logic blocks in a time shared manner. A data bus arrangement is disclosed which can be utilized to interconnect a plurality of ports with each other and which utilize Josephson junction devices. Each of a plurality of ports represents the output from a computer or other logic circuit and these outputs represent inputs on control lines associated with each Josephson device which switch it. Each Josephson device is separately energized from its own current source and, upon switching, diverts current down a transmission line which has an impedance, Zo. In a single wire-over ground plane embodiment, all of the transmission lines are connected to a single node in a star arrangement. A terminating resistor which terminates each of the lines in a value of resistance equal to Zo is disposed in series in the transmission line and is intended to absorb signals coming from any port so there is no reflection of incoming signals back along the transmission line. From the node at which all the transmission lines are connected, a signal generated at one port, for example, passes in parallel to each of the other ports. There, depending on whether or not a sensing Josephson junction which is associated with each transmission line is enabled, the signal is sensed at a selected sensing junction. The present approach utilizes the fact that, when an input junction is in the unactuated state, it represents a short circuit presenting no internal impedance to the incoming current which can then be absorbed in a resistance which, in spite of the presence of the switchable device, remains as a termination equal in resistance to the characteristic impedance of the transmission line. A double wire over ground plane or a wire above and below ground plane embodiment is also shown, wherein the two wires or transmission lines associated with each input port are connected to a pair of nodes. Each line has the same characteristic impedance and each is terminated by a resistance equal to the characteristic impedance. In this arrangement, the resulting signal strength available for sensing can be two times the strength of the single wire embodiment, due to a reversal of the transmission line in the neighborhood of a sense gate.
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公开(公告)号：DE69115866D1
公开(公告)日：1996-02-08
申请号：DE69115866
申请日：1991-10-10
Applicant: IBM
Inventor： SCHLIG EUGENE STEWART , YAO YING LUH
Abstract: An electronic imaging system develops red, green and blue images of a document in a single pass of the document through the system. The system includes an image sensor which has three time delay and integration (TDI) sensor arrays. Each sensor array is configured to have two optically masked rows of charge coupled devices (CCD's) for every row of CCD's that is used for imaging. The sensor arrays are arranged so that the first row of imaging CCD's on any two successive arrays are separated by a distance of an integer, K, times three times the height of a picture element (pel) of the image of the document that is projected onto the image sensor, plus or minus one pel height. The spectral component of the image of the document that is projected onto the image sensor is changed in sequence from red, to green, to blue. As the spectral component projected onto the image sensor is changed, the image of the document is scanned down the image sensor by a distance of one pel height. By this scheme, each line of pels in the document is imaged in each of the sensor arrays in a respectively different spectral component. A document may be imaged in all three colors in a single pass through the system without having dedicated filters for each of the separate sensor arrays.
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公开(公告)号：DE69115866T2
公开(公告)日：1996-07-11
申请号：DE69115866
申请日：1991-10-10
Applicant: IBM
Inventor： SCHLIG EUGENE STEWART , YAO YING LUH
Abstract: An electronic imaging system develops red, green and blue images of a document in a single pass of the document through the system. The system includes an image sensor which has three time delay and integration (TDI) sensor arrays. Each sensor array is configured to have two optically masked rows of charge coupled devices (CCD's) for every row of CCD's that is used for imaging. The sensor arrays are arranged so that the first row of imaging CCD's on any two successive arrays are separated by a distance of an integer, K, times three times the height of a picture element (pel) of the image of the document that is projected onto the image sensor, plus or minus one pel height. The spectral component of the image of the document that is projected onto the image sensor is changed in sequence from red, to green, to blue. As the spectral component projected onto the image sensor is changed, the image of the document is scanned down the image sensor by a distance of one pel height. By this scheme, each line of pels in the document is imaged in each of the sensor arrays in a respectively different spectral component. A document may be imaged in all three colors in a single pass through the system without having dedicated filters for each of the separate sensor arrays.
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公开(公告)号：DE2324965A1
公开(公告)日：1974-01-10
申请号：DE2324965
申请日：1973-05-15
Applicant: IBM
Inventor： YAO YING LUH
IPC: G11C11/419 , G11C7/02 , G11C11/404 , G11C11/409 , G11C11/4091 , G11C11/4099 , G11C7/00
Abstract: A sensing circuit which is responsive to binary information represented by the level of charge in a capacitor is disclosed. The circuit comprises a differential amplifier; the nodes of which are connected to bucket brigade sense amplifier arrangements which are in turn connected to bit lines to which a plurality of memory device which store information in the form of charge are connected. Each bit line portion connected to the buck
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