公开(公告)号：EP0793237A3

公开(公告)日：1998-05-27

申请号：EP96306481

申请日：1996-09-06

Applicant: IBM

Inventor： KATOH DAISUKE ,  KIRIHATA TOSHIAKI ,  YOSHIBA MUNEHIRO

IPC: G11C11/409 ,  G11C7/10 ,  G11C11/4091 ,  G11C11/4094

CPC classification number: G11C11/4094 ,  G11C7/1006 ,  G11C11/4091 ,  G11C2207/002 ,  G11C2207/005

Abstract: An improved data sense is provided for a DRAM in which each bit line pair is coupled through a pair of high-resistance pass gates 163 to a sense amp 166. During sense, the high-resistance pass gates act in conjunction with the charge stored on the bit line pair as, effectively, a high-resistance passive load for the sense amp. A control circuit selectively switches on and off bit line equalization coincident with selectively passing either the equalization voltage or set voltages to the sense amp and an active sense amp load. Further, after it is set, the sense amp is selectively connected to LDLs through low-resistance column select pass gates 176. Therefore, the sense amp quickly discharges one of the connected LDL pair while the bit line voltage remains essentially unchanged. Thus, data is passed from the sense amp to a second sense amplifier and off chip. After data is passed to the LDLs, the control circuit enables the active sense amp load to pull the sense amp high side to a full up level.

公开(公告)号：DE69625038D1

公开(公告)日：2003-01-09

申请号：DE69625038

申请日：1996-09-06

Applicant: TOSHIBA KAWASAKI KK ,  IBM

Inventor： KATOH DAISUKE ,  KIRIHATA TOSHIAKI ,  YOSHIBA MUNEHIRO

IPC: G11C11/409 ,  G11C7/10 ,  G11C11/4091 ,  G11C11/4094

Abstract: The DRAM comprises an array of memory cells in rows and columns. A word line is provided in each row and a bit line is provided in each column. Each bit line pair is coupled through a pair of high-resistance pass gates to a sense amp. During sense, the high-resistance pass gates act in conjunction with the charge stored on the bit line pair as, effectively, a high-resistance passive load for the sense amp. A control circuit selectively switches on and off bit line equalization coincident with selectively passing either the equalization voltage or set voltages to the sense amp and an active sense amp load. Further, after it is set, the sense amp is selectively connected to LDLs through low-resistance column select pass gates. Therefore, the sense amp quickly discharges one of the connected LDL pair while the bit line voltage remains essentially unchanged. Thus, data is passed from the sense amp to a second sense amplifier and off chip. After data is passed to the LDLs, the control circuit enables the active sense amp load to pull the sense amp high side to a full up level.

公开(公告)号：DE69625038T2

公开(公告)日：2003-07-10

申请号：DE69625038

申请日：1996-09-06

Applicant: TOSHIBA KAWASAKI KK ,  IBM

Inventor： KATOH DAISUKE ,  KIRIHATA TOSHIAKI ,  YOSHIBA MUNEHIRO

IPC: G11C11/409 ,  G11C7/10 ,  G11C11/4091 ,  G11C11/4094

Abstract: The DRAM comprises an array of memory cells in rows and columns. A word line is provided in each row and a bit line is provided in each column. Each bit line pair is coupled through a pair of high-resistance pass gates to a sense amp. During sense, the high-resistance pass gates act in conjunction with the charge stored on the bit line pair as, effectively, a high-resistance passive load for the sense amp. A control circuit selectively switches on and off bit line equalization coincident with selectively passing either the equalization voltage or set voltages to the sense amp and an active sense amp load. Further, after it is set, the sense amp is selectively connected to LDLs through low-resistance column select pass gates. Therefore, the sense amp quickly discharges one of the connected LDL pair while the bit line voltage remains essentially unchanged. Thus, data is passed from the sense amp to a second sense amplifier and off chip. After data is passed to the LDLs, the control circuit enables the active sense amp load to pull the sense amp high side to a full up level.