公开(公告)号：DE1499694A1

公开(公告)日：1970-12-23

申请号：DE1499694

申请日：1966-06-07

Applicant: IBM

Inventor： HSIAO MU-YUE ,  YUE SIH KWANG

IPC: H04L1/00 ,  G08B29/00

Abstract: 1,087,685. Error correction. INTERNATIONAL BUSINESS MACHINES CORPORATION. June 2,1966 [June 7, 1965], No. 24603/66. Heading G4A. Error correction apparatus using a feedbackshift register for correcting- input data and buffer means for the data, accepts parallel data input. A plurality of input channels, carrying a block of data. in serial-parallel form comprising: data and. check bitsaccording to a cyclic code,. feeds a set of buffers (one per channel) and a shiftregister having flip-flops, exclusive-or; gates and a plurality of feedback channels.. When. the block has been received, the buffers are shifted, out in synehronism with. recycling of the shift register, AND gates (one per channel) recognise particular bit configurations in the shift register, and control exclusive-or gates to invert erroneous bits (single errors) as they emerge from the buffers: Any such inversion is accompanied. by resetting of all set stages of the shift register. The block of data applied to the input channels above originally obtained its check bits from a further identical shift-register. A further embodiment for correcting burst errorsis described briefly.