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    COMMUNICATION SYSTEM COMPRISING OVERLAYED MULTIPLE-ACCESS TRANSMISSION NETWORKS
    3.
    发明专利
    COMMUNICATION SYSTEM COMPRISING OVERLAYED MULTIPLE-ACCESS TRANSMISSION NETWORKS 未知

    公开(公告)号：DE3572103D1

    公开(公告)日：1989-09-07

    申请号：DE3572103

    申请日：1985-02-28

    Applicant: IBM

    Inventor： KELLER HEINZ JOSEF ,  MUELLER JOHANN RUDOLF ,  ROTHAUSER ERNST HANS ,  ZURFLUH ERWIN ALEX

    IPC: H04B10/20 ,  H04L12/28 ,  H04L11/16

    Abstract: In a communication system providing multiple access to transmission facilities for a plurality of stations (17, 21), two separate networks (11, 13) are provided: One is a token ring (11) on which access tokens and data are transmitted, the other is a high-speed optical fiber transmission ring (13) on which only large-volume data blocks are transmitted between particular stations (21) which are attached to both rings, but no access information. A token manager (27) in the token ring (11) provides at regular intervals particular tokens that are only used by the particular stations (21) for obtaining access to the high-speed ring (13), but also provides other tokens for regulating access to the token ring (11) for other stations (17). Special access modes (23) are provided which allow to connect the particular stations (21) to the high-speed ring (13) without extending its length.

    6.
    发明专利
    未知

    公开(公告)号：DE3481472D1

    公开(公告)日：1990-04-05

    申请号：DE3481472

    申请日：1984-12-21

    Applicant: IBM

    Inventor： ZURFLUH ERWIN ALEX

    IPC: H03L7/06 ,  H03L7/081 ,  H04L7/033 ,  H03L7/00

    Abstract: A phase locked loop (PLL) arrangement comprising a local crystal oscillator (23) and a tapped delay chain (15) of analog delay elements (17). Connected to the delay chain taps are a flash register (25) consisting of latches which store the tap signal values at each data signal transition, and an output multiplexer (37) for selecting one of the tap signals as phase shifted output clock. Contents of the flash register are encoded by an encoder (33) which furnishes a value representing the phase offset between data signal and local clock signal. By a look-up table (41), the phase offset is converted to a phase selection value controlling the output multiplexer. The delay chain serves two purposes: Phase offset detection and clock signal phase shifting. No sampling or control signals are used which have a higher frequency than that of the system clock.

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