公开(公告)号：DE3275692D1

公开(公告)日：1987-04-16

申请号：DE3275692

申请日：1982-12-28

Applicant: IBM ,  IBM FRANCE

Inventor： AMBOISE MODESTE ,  DEMANGE MICHEL ,  LEBIZAY GERARD ,  MUNIER JEAN-MARIE ,  PEYRONNENC MICHEL HENRI PAUL

IPC: H04L5/22 ,  H04J3/06 ,  H04L12/42 ,  H04Q11/04 ,  H04L11/16 ,  H04L7/00

Abstract: The contents of input time-division channels on a closed-loop link (10LO, 10HI) are stored in a memory (173) at the address supplied by an input address counter (IAC) controlled by an incoming timing signal (2MCR). The memory is read out under control of an output address counter (OAC) controlled by an outgoing timing signal (2MCT). Each time interval is divided into one read period and two write periods. Means (186) are provided to select one of the two write periods dependent on the phase relationship between the incoming and outgoing timing signals. The units connected in series by means of the closed-loop link receive a timing signal circulating on a timing loop (15) that is closed by a master timing device (13). Slave timing devices (18) inserted in the timing loop regenerate the timing signals circulating thereon and check same.