公开(公告)号：DE60215513D1

公开(公告)日：2006-11-30

申请号：DE60215513

申请日：2002-08-06

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： DOBUZINSKY MARK ,  KHAN ALI ,  LIU C ,  WENSLEY PAUL ,  YU CHIENFAN

IPC: H01L21/8242 ,  H01L21/3213 ,  H01L21/60 ,  H01L21/8234

Abstract: A method of fabricating an integrated circuit chip having a first region of a first layout rule and a second region of a second layout rule. The method includes using a first material to establish a first hard mask pattern in only the first region and using a second material to establish a second hard mask pattern on top of the first hard mask pattern. The second material is additionally used to establish a third hard mask pattern in the second region.

公开(公告)号：DE60215513T2

公开(公告)日：2007-07-05

申请号：DE60215513

申请日：2002-08-06

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： DOBUZINSKY MARK ,  KHAN ALI ,  LIU C ,  WENSLEY PAUL ,  YU CHIENFAN

IPC: H01L21/8242 ,  H01L21/3213 ,  H01L21/60 ,  H01L21/8234

Abstract: A method of fabricating an integrated circuit chip having a first region of a first layout rule and a second region of a second layout rule. The method includes using a first material to establish a first hard mask pattern in only the first region and using a second material to establish a second hard mask pattern on top of the first hard mask pattern. The second material is additionally used to establish a third hard mask pattern in the second region.