公开(公告)号：GB2321984A

公开(公告)日：1998-08-12

申请号：GB9725507

申请日：1997-12-02

Applicant: IBM ,  MOTOROLA INC

Inventor： MALLICK SOUMMYA ,  PATEL RAJESH BHIKHUBHAI ,  LOPER ALBERT J ,  JESSANI ROMESH M

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/312

Abstract: A processor includes execution circuitry and a set of registers GPR26-31 which are each capable of storing a data word. A multiple-register instruction specifying a plurality of data words that are to be transferred to or from a corresponding plurality of registers within the set of registers is dispatched to the execution circuitry. In response to receipt of the multiple-register instruction, the execution circuitry executes it such that at least two data words among the plurality of data words are written to or read from at least two corresponding registers during a single cycle of the processor.