公开(公告)号：JPH10228376A

公开(公告)日：1998-08-25

申请号：JP34310697

申请日：1997-12-12

Applicant: IBM ,  MOTOROLA INC

Inventor： SUUMUYA MALIK ,  RAJESH B PATEL ,  LOPER ALBERT JOHN ,  ROMESHU M JESANI

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/312

Abstract: PROBLEM TO BE SOLVED: To enable access to registers and to effective execute a multiple- register instruction by dispatching an instruction that specifies data words written registers. SOLUTION: A sequencer device 17 stores data in registers GPR 22 and FPR 25 and take the data out of them. A branching device 11 receives a branch instruction and a signal indicating the current state of a processor 10 from the sequencer device 17. The branching device 11 responds to those branch instruction and signal and outputs a signal indicating a proper memory address to the sequencer device 17. The sequencer device 17 once receiving those signals from the branching device 11 takes a series of indicated instructions out of an instruction cache 27. Then the sequencer device 17 dispatches the instructions fetched from the instruction cache 27 selectively to selected execution devices among 11 to 16. Each execution device executes instructions of specific classes.

公开(公告)号：JPH10214226A

公开(公告)日：1998-08-11

申请号：JP29188297

申请日：1997-10-24

Applicant: IBM

Inventor： RAJESH B PATEL

IPC: G06F12/08

Abstract: PROBLEM TO BE SOLVED: To improve memory performance by removing a certain class among old lines in a 2nd level(L2) cache during the processing of cache access. SOLUTION: A processor 12 issues a memory request to a multilevel memory system provided with a 1st level(L1) cache 14, L2 cache 20 and main memory 22. When hit is to occur inside an L1 cache tag 15 because of cache access started by store, the store is executed to the cache line in an L1 cache array 16, and that cache line is marked as corrected. A table index concerning that cache line is started by an L2 cache tag 23, and that cache line is invalidated inside an L2 cache array 25. Thus, this old, therefore, unwanted cache line is removed from the L2 cache 20.

公开(公告)号：JPH10161872A

公开(公告)日：1998-06-19

申请号：JP18112897

申请日：1997-07-07

Applicant: IBM

Inventor： RAJESH B PATEL ,  SOUNMIYA MALIK

IPC: G06F9/315 ,  G06F9/312 ,  G06F9/38 ,  G06F12/04

Abstract: PROBLEM TO BE SOLVED: To increase positioning hardware and positioning registers in quantity by reading a 1st and a 2nd word out of a cache, rotating the 1st and 2nd words, and storing at least one byte each of the 1st and 2nd words in a rename register. SOLUTION: The 1st and 2nd words are supplied from the cache to a byte rotator 500, which rotates bytes in the 1st and 2nd the words supplied from the cache, outputs the data to four 8-bit data lines 500a to 500d, and adapts the data so as to position them at arbitrary bytes ROa to ROd of the rename register RO. Then one byte each of the 1st and 2nd words is temporarily stored in the rename register RO. Consequently, the positioning hardware and positioning registers can be increased in quantity, and consequently many positioning registers can be formed on a chip.