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公开(公告)号：CA2159888A1
公开(公告)日：1996-04-06
申请号：CA2159888
申请日：1995-10-04
Applicant: IBM , MOTOROLA INC
Inventor： ROSSBACH PAUL C , KAU CHIN-CHENG , LEVITAN DAVID S
Abstract: An improved method of addressing within a pipelined processor having an address bit width of m + n bits is disclosed, which includes storing m high order bits corresponding to a first range of addresses, which encompasses a selected plurality of data executing within the pipelined processor. The n low order bits of addresses associated with each of the selected plurality of data are also stored. After determining the address of a subsequent datum to be executed within the processor, the subsequent datum is fetched. In response to fetching a subsequent datum having an address outside of the first range of addresses, a status register is set to a first of two states to indicate that an update to the first address register is required. In response to the status register being set to the second of the two states, the subsequent datum is dispatched for execution within the pipelined processor. The n low order bits of the subsequent datum are then stored, such that memory required to store addresses of instructions executing within the pipelined processor is thereby decreased.
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公开(公告)号：GB2284912B
公开(公告)日：1998-04-22
申请号：GB9424323
申请日：1994-12-01
Applicant: MOTOROLA INC
Inventor： JAIN DANNY K , LEVITAN DAVID S , ROSSBACH PAUL C
IPC: G06F9/38
Abstract: A data processor (12) has a branch prediction unit (28) that predicts conditional branch instructions and a control unit (70) therein that monitors the number of unresolved branch instructions. This control unit selectively allows the data processor to fetch the instructions indicated by the branch prediction unit from an external memory system depending upon the number of unresolved branch instructions. The particular threshold number of unresolved branch instructions is user programmable. The data processor thereby limits its bus accesses to those occasions when it is reasonably sure that it will need the indicated instructions.
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公开(公告)号：GB2284912A
公开(公告)日：1995-06-21
申请号：GB9424323
申请日：1994-12-01
Applicant: MOTOROLA INC
Inventor： JAIN DANNY K , LEVITAN DAVID S , ROSSBACH PAUL C
IPC: G06F9/38
Abstract: A data processor has a branch prediction unit (28) that predicts conditional branch instructions and a control unit (70) therein that monitors the number of unresolved branch instructions. This control unit selectively allows the data processor to fetch the instructions indicated by the branch prediction unit from an external memory system depending upon the number of unresolved branch instructions. The particular threshold number of unresolved branch instructions is user programmable. The data processor thereby limits its bus accesses to those occasions when it is reasonably sure that it will need the indicated instructions.
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公开(公告)号：GB2267589B
公开(公告)日：1997-01-15
申请号：GB9310444
申请日：1993-05-20
Applicant: MOTOROLA INC
Inventor： ROSSBACH PAUL C
Abstract: A method and apparatus for performing integer and floating-point divide operations using a single modified SRT divider in a data processor. The floating-point and integer division is performed using SRT division on normalized positive mantissas (dividend and divisor). Integer division shares portions of the floating point circuitry, however, the sequence of operations is modified during the performance of an integer divide operation. The SRT divider performs a sequence of operations before and after an iteration loop to re-configure an integer divisor and dividend into a data path representation which the SRT algorithm requires for floating-point mantissas. During the iteration loop, quotient bits are selected and used to generate intermediate partial remainders. The quotient bits are also input to quotient registers which accumulate the final quotient mantissa. A full mantissa adder is used to generate a final remainder.
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Patent Agency Ranking
公开(公告)号：IE940854A1
公开(公告)日：1995-05-03
申请号：IE940854
申请日：1994-11-01
Applicant: MOTOROLA INC
Inventor： ROSSBACH PAUL C , LEVITAN DAVID S
IPC: G06F9/38
Abstract: A data processor (10) has branch prediction circuitry (18) to predict a conditional branch instruction before the condition on which the instruction is based is known. The branch prediction circuitry operates in one of two user selectable modes: (1) dynamic branch prediction; or (2) static branch prediction. In the dynamic branch predition mode, the prediction is based upon a branch state maintained for each branch instruction. Each branch state may be updated after the data processor determines if the prediction was correct. In the static branch prediction mode, the branch prediction is based on one or more bits embedded in the branch instruction. The data processor may or may not update the branch state of each branch instruction during this second mode as desired by the user.
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公开(公告)号：GB2283595B
公开(公告)日：1998-06-03
申请号：GB9420379
申请日：1994-10-10
Applicant: MOTOROLA INC
Inventor： ROSSBACH PAUL C , LEVITAN DAVID S
IPC: G06F9/38
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公开(公告)号：IE940855A1
公开(公告)日：1995-06-28
申请号：IE940855
申请日：1994-11-01
Applicant: MOTOROLA INC
Inventor： JAIN DANNY K , LEVITAN DAVID S , ROSSBACH PAUL C
IPC: G06F9/38
Abstract: A data processor (12) has a branch prediction unit (28) that predicts conditional branch instructions and a control unit (70) therein that monitors the number of unresolved branch instructions. This control unit selectively allows the data processor to fetch the instructions indicated by the branch prediction unit from an external memory system depending upon the number of unresolved branch instructions. The particular threshold number of unresolved branch isntructions is user programmable. The data processor thereby limits its bus accesses to those occasions when it is reasonably sure that it will need the indicated instructions.
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公开(公告)号：GB2283595A
公开(公告)日：1995-05-10
申请号：GB9420379
申请日：1994-10-10
Applicant: MOTOROLA INC
Inventor： ROSSBACH PAUL C , LEVITAN DAVID S
Abstract: A data processor (10) (Fig.1) has branch prediction circuitry 62 - 76 to predict a conditional branch instruction address before the condition on which the instruction is based is known. The branch prediction circuitry operates in one of two user selectable modes: dynamic branch prediction or static branch prediction. In the dynamic mode, the prediction is based upon a branch state history maintained at 62 for each branch instruction. Each branch state may be updated after the data processor determines if the prediction was correct. In the static mode, the branch prediction is based on one or more bits embedded in the branch instruction. The data processor may or may not update the branch state of each branch instruction during this second mode, as desired by the user. In either mode the predicted address is selected from the output of an incrementer 72 or a calculator 74, by a multiplexer 68.
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公开(公告)号：GB2267589A
公开(公告)日：1993-12-08
申请号：GB9310444
申请日：1993-05-20
Applicant: MOTOROLA INC
Inventor： ROSSBACH PAUL C
Abstract: A method and apparatus for performing integer and floating-point divide operations using a single modified SRT divider 30 in a data processor 10. The floating-point and integer division is performed using SRT division on normalized positive mantissas (divided and divisor). Integer division shares portions of the floating point circuitry, however, the sequence of operations is modified during the performance of an integer divide operation. The SRT divider 30 performs a sequence of operations before and after an iteration loop to re-configure an integer divisor and dividend into a data path representation which the SRT algorithm requires for floating-point mantissas. During the iteration loop, quotient bits are selected and used to generate intermediate partial remainders. The quotient bits are also input to quotient registers 66 which accumulate the final quotient mantissa. A full mantissa adder is used to generate a final remainder.
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