公开(公告)号：JP2000035917A

公开(公告)日：2000-02-02

申请号：JP11010799

申请日：1999-04-16

Applicant: IBM ,  MOTOROLA INC

Inventor： THOMAS ALBERT PETERSON ,  JAMES NOLAN HAADEEJI JR

IPC: G06F12/08 ,  G06F12/04 ,  G06F13/36

Abstract: PROBLEM TO BE SOLVED: To perform full gathering of data transfer from a processor to a system bus without adding logic of many levels nor lowering a processor operation frequency by dividing gatherable combinations and performing gathering on plural stages that parallelly operate. SOLUTION: The arrangement of input transaction to a transaction to a transaction queue 202 is controlled by a write enable logic 204 and the logic 204 decides an available item and selects an item to which input transaction is loaded by forming an appropriate enable signal. It is possible to shift an item in the queue 202 or to perform other operations in response to a signal that is received from item control logic 206. The logic 206 controls a queue operation such as item shifting for performing FIFO execution of the queue 202 when data transfer of transaction that is made a queue is completed on a system bus.

公开(公告)号：JP2000082036A

公开(公告)日：2000-03-21

申请号：JP14111099

申请日：1999-05-21

Applicant: IBM

Inventor： ALEXANDER EDWARD OKUPISHU ,  THOMAS ALBERT PETERSON

IPC: G06F13/16 ,  G06F13/14 ,  G06F13/376 ,  G06F13/42

Abstract: PROBLEM TO BE SOLVED: To provide a means which eliminates the retrial of an operation during the collision of immediately preceding adjacent address coincidence (PAAM) windows by preparing a step where a system bus is snooped, a step where it's decided whether a 1st operation collides with its immediately preceding operation and a step where a null transaction type is inserted. SOLUTION: The communication is performed among the processors A 104, B 106 and C 108 of a data processing system 100 and a system memory 110 via a system bus 102. This method eliminates the collision of addresses on the bus 102 and includes a step where the bus 102 is snooped, a step where it's decided whether a 1st operation collides with its immediately preceding operation and a step where a null transaction type is inserted. If the PAAM windows of the same addresses are detected, a non-master processor switches the issued next transaction type to a null type.