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公开(公告)号：DE69430870T2
公开(公告)日：2003-03-13
申请号：DE69430870
申请日：1994-07-28
Applicant: IBM , PAILLET GUY
Inventor： BOULET JEAN YVES , GODEFROY CATHERINE , STEIMLE ANDRE , LOUIS DIDIER , PAILLET GUY , TANNHOF PASCAL
Abstract: In a neural network comprised of a plurality of neuron circuits, there is disclosed an improved neuron circuit architecture (11) that generates local result signals, e.g. of the fire (F) type and a local output signal of the distance or category type. The neuron circuit which is connected to buses which transport input data (e.g. the input category) and control signals includes the following circuits. A multi-norm distance evaluation circuit (300) calculates the distance D between the input vector (A) and the prototype vector (B) stored in a R/W (weight) memory circuit (250). A distance compare circuit (300) compares the distance D with either the actual influence field (AIF) of the stored prototype vector or the lower limit thereof (MinIF) to generate first and second intermediate signals (LT, LTE). An identification circuit (400) processes the said intermediate result signals, the input category signal (CAT), the local category signal (C) and a feedback signal (OR) to generate the local result signals which represent the response of a neuron circuit to the presentation of an input vector. A minimum distance determination circuit (500) is adapted to determine the minimum distance Dmin among all the distances calculated by all the neuron circuits of the neural network to generate a local output signal (NOUT) of the distance type. The same processing applies to categories. The feed-back signal which is collectively generated by all the neuron circuits results of ORing all the local distances/categories. A daisy chain circuit (600) is serially connected to the corresponding daisy chain circuits of the two adjacent neuron circuits to structure the neural network as a chain. Its role is to determine the neuron circuit state: free (in particular, the first free in the chain) and engaged. Finally, a context circuitry (100/150) is capable to allow or not the neuron circuit to participate with the other neuron circuits in the generation of the said feed-back signal.
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公开(公告)号：DE69430744D1
公开(公告)日：2002-07-11
申请号：DE69430744
申请日：1994-07-28
Applicant: IBM , PAILLET GUY
Inventor： STEIMLE ANDRE , PAILLET GUY , TANNHOF PASCAL
Abstract: There is disclosed the architecture of a neural semiconductor chip (10) first including a neuron unit (11(#)) comprised of a plurality of neuron circuits (11-1, ...) fed by different buses transporting data such as the input vector data, set-up parameters, ... and control signals. Each neuron circuit (11) includes means for generating local result (F, ... ) signals of the "fire" type and a local output signal (NOUT) of the distance or category type on respective buses (NR-BUS, NOUT-BUS). An OR circuit (12) performs an OR function for all corresponding local result and output signals to generate respective first global result (R*) and output (OUT*) signals on respective buses (R*-BUS, OUT*-BUS) that are merged in an on-chip common communication bus (COM*-BUS) shared by all neuron circuits of the chip. An additional OR function is then performed between all corresponding first global result and output signals to generate second global result (R**) and output (OUT**) signals, preferably by dotting on an off-chip common communication bus (COM**-BUS) in the driver block (19). This latter bus is shared by all the neural chips that are connected thereon to incorporate a neural network of the desired size. In the chip, a multiplexer (21) may select either the first or second global output signal to be reinjected in all neuron circuits of the neural network as a feed-back signal depending on the chip operates in a single or multi-chip environment via a feed-back bus (OR-BUS). The feedback signal results of a collective processing of all the local signal.
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公开(公告)号：DE69430529D1
公开(公告)日：2002-06-06
申请号：DE69430529
申请日：1994-07-28
Applicant: IBM , PAILLET GUY
Inventor： STEIMLE ANDRE , GUY PAILLET , TANNHOF PASCAL , GODEFROY CATHERINE
Abstract: A daisy chain circuit (600) is placed in each neuron circuit of a neural network. Each daisy chain circuit is serially connected to the two adjacent neuron circuits, so that all the neuron circuits are structured as a chain. Its main role is to distinguish between the two possible states of the neuron circuit: engaged or free and moreover to identify the first free "or ready to learn" neuron circuit in the chain. This distinction is based on the respective values of the input (DCI) and output (DCO) signals of the daisy chain circuit. The ready to learn neuron circuit is the only neuron circuit of the neural network whose said input and output signals are complementary to each other. It is built around a 1-bit register (601) controlled by a store enable signal (ST) which is set active at initialization or during the learning phase when a new neuron circuit must be engaged. The input terminal of the first daisy chain circuit in the chain is connected to a first logic value, so that it is the ready to learn neuron circuit by construction after initialization. After initialization, all the registers of the chain are set to a second logic value. In the learning phase, the 1-bit register contents of the ready to learn neuron circuit is set to the said first logic value by the store enable signal, it is said "engaged". The following neuron circuit in the chain then becomes the new ready to learn neuron circuit. In addition, the daisy chain circuit is adapted to generate various control signals e.g. the control signal (RS) that allows to load the input vector components in the weight memory of only the ready to learn neuron circuit during the recognition phase.
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4.发明专利
公开(公告)号：CA2149479A1
公开(公告)日：1996-01-29
申请号：CA2149479
申请日：1995-05-16
Applicant: IBM , PAILLET GUY
Inventor： PAILLET GUY , STEIMLE ANDRE , TANNHOF PASCAL
Abstract: There is disclosed the architecture of a neural semiconductor chip first inc luding a neuron unit comprised of a plurality of neuron circuits fed by different buses tran sporting data such as the input vector data, set-up parameters, and control signals. Each neuron circuit includes means for generating local result signals of the "fire" type and a local output signal of the distance or category type on respective buses. An OR circuit p erforms an OR function for all corresponding local result and output signals to generate r espective first global result and output signals on respective buses that are merged in an o n-chip common communication bus shared by all neuron circuits of the chip. An additional O R function is then performed between all corresponding first global result and output sign als to generate second global result and output signals, preferably by dotting on an off-chi p common communication bus in the driver block. This latter bus is shared by all the neural chips that are connected thereon to incorporate a neural network of the desired si ze. In the chip, a multiplexer may select either the first or second global output signal to be reinjected in all neuron circuits of the neural network as a feed-back signal depending on the chip operates in a single or multi-chip environment via a feed-backbus. The feedb ack signal results of a collective processing of all the local signal.
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公开(公告)号：DE69430744T2
公开(公告)日：2003-01-30
申请号：DE69430744
申请日：1994-07-28
Applicant: IBM , PAILLET GUY
Inventor： STEIMLE ANDRE , PAILLET GUY , TANNHOF PASCAL
Abstract: There is disclosed the architecture of a neural semiconductor chip (10) first including a neuron unit (11(#)) comprised of a plurality of neuron circuits (11-1, ...) fed by different buses transporting data such as the input vector data, set-up parameters, ... and control signals. Each neuron circuit (11) includes means for generating local result (F, ... ) signals of the "fire" type and a local output signal (NOUT) of the distance or category type on respective buses (NR-BUS, NOUT-BUS). An OR circuit (12) performs an OR function for all corresponding local result and output signals to generate respective first global result (R*) and output (OUT*) signals on respective buses (R*-BUS, OUT*-BUS) that are merged in an on-chip common communication bus (COM*-BUS) shared by all neuron circuits of the chip. An additional OR function is then performed between all corresponding first global result and output signals to generate second global result (R**) and output (OUT**) signals, preferably by dotting on an off-chip common communication bus (COM**-BUS) in the driver block (19). This latter bus is shared by all the neural chips that are connected thereon to incorporate a neural network of the desired size. In the chip, a multiplexer (21) may select either the first or second global output signal to be reinjected in all neuron circuits of the neural network as a feed-back signal depending on the chip operates in a single or multi-chip environment via a feed-back bus (OR-BUS). The feedback signal results of a collective processing of all the local signal.
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Patent Agency Ranking
公开(公告)号：CA2149478A1
公开(公告)日：1996-01-29
申请号：CA2149478
申请日：1995-05-16
Applicant: IBM , PAILLET GUY
Inventor： BOULET JEAN YVES , LOUIS DIDIER , GODEFROY CATHERINE , PAILLET GUY , STEIMLE ANDRE , TANNHOF PASCAL
Abstract: In a neural network comprised of a plurality of neuron circuits, there is disclosed an improved neuron circuit architecture (11) that generates local result signals, e.g. of the fire (F) type and a local output signal of the distance or category type. The neuron circuit which is connected to buses which transport input data (e.g. the input category) and control signals includes the following circuits. A multi-norm distance evaluation circuit (300) calculates the distance D between the input vector (A) and the prototype vector (B) stored in a R/W (weight) memory circuit (250). A distance compare circuit (300) compares the distance D with either the actual influence field (AIF) of the stored prototype vector or the lower limit thereof (MinIF) to generate first and secondintermediate signals (LT, LTE). An identification circuit (400) processes the said intermediate result signals, the input category signal (CAT), the local category signal (C) and a feedback signal (OR) to generate the local result signals which represent the response of a neuron circuit to the presentation of an input vector. A minimum distance determination circuit (500) is adapted to determine the minimum distance Dmin among all the distances calculated by all the neuron circuits of the neural network to generate a local output signal (NOUT) of the distance type. The same processing applies to categories . The feed-back signal which is collectively generated by all the neuron circuits results of ORing all the local distances/categories. A daisy chain circuit (600) is serially connected to the corresponding daisy chain circuits of the two adjacent neuron circuits to structure the neural network as a chain. Its role is to determine the neuron circuit state: free (in particular, the first free in the chain) and engaged. Finally, a context circuitry (100/150) is capable to allow or not the neuron circuit to participate with the other neuron circuits in the generation of the said feedback signal.
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公开(公告)号：DE69430529T2
公开(公告)日：2003-01-16
申请号：DE69430529
申请日：1994-07-28
Applicant: IBM , PAILLET GUY
Inventor： STEIMLE ANDRE , GUY PAILLET , TANNHOF PASCAL , GODEFROY CATHERINE
Abstract: A daisy chain circuit (600) is placed in each neuron circuit of a neural network. Each daisy chain circuit is serially connected to the two adjacent neuron circuits, so that all the neuron circuits are structured as a chain. Its main role is to distinguish between the two possible states of the neuron circuit: engaged or free and moreover to identify the first free "or ready to learn" neuron circuit in the chain. This distinction is based on the respective values of the input (DCI) and output (DCO) signals of the daisy chain circuit. The ready to learn neuron circuit is the only neuron circuit of the neural network whose said input and output signals are complementary to each other. It is built around a 1-bit register (601) controlled by a store enable signal (ST) which is set active at initialization or during the learning phase when a new neuron circuit must be engaged. The input terminal of the first daisy chain circuit in the chain is connected to a first logic value, so that it is the ready to learn neuron circuit by construction after initialization. After initialization, all the registers of the chain are set to a second logic value. In the learning phase, the 1-bit register contents of the ready to learn neuron circuit is set to the said first logic value by the store enable signal, it is said "engaged". The following neuron circuit in the chain then becomes the new ready to learn neuron circuit. In addition, the daisy chain circuit is adapted to generate various control signals e.g. the control signal (RS) that allows to load the input vector components in the weight memory of only the ready to learn neuron circuit during the recognition phase.
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公开(公告)号：DE69430528D1
公开(公告)日：2002-06-06
申请号：DE69430528
申请日：1994-07-28
Applicant: IBM , PAILLET GUY
Inventor： BOULET JEAN-YVES , TANNHOF PASCAL , PAILLET GUY
Abstract: In a neural network comprised of a plurality of N neuron circuits, each having calculated the distance (D1, ... , D4) coded on p bits (D1 = d11 ... d41) between an input vector and the prototype vector stored in the weight memory thereof, there is disclosed an aggregate circuit (517) comprised of N search/sort circuits (502-1, ..., 502-4) each being placed in a neuron circuit. The search/sort circuit is adapted to determine the minimum distance among said calculated distances. Each search/sort circuit (502-1) is comprised of p elementary base units (510-11 to 510-41) connected in series and disposed in a column direction. The distance bit signals of the same bit rank are applied to said base units according a line direction. As a consequence, the base units of the aggregate circuit are organized in a matrix. The feedback signal corresponds to the signal obtained by performing an OR function in an OR gate (12.1) between all the local output signals generated by the base units of a determined line. The search process is based on the search of zeroes in the distance bit signals, from the MSB's to the LSB's. If a zero is found in a determined line, all the columns which have a one in this line are excluded from the following search. The process is continued until it remains only one distance: the searched minimum distance, that is finally available at the output of the said OR circuit. The above described search/sort circuit can be significantly improved by adjoining a latch based circuit so that the aggregate circuit is now capable to sort the remaining distances in an increasing order.
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公开(公告)号：DE69430528T2
公开(公告)日：2003-01-02
申请号：DE69430528
申请日：1994-07-28
Applicant: IBM , PAILLET GUY
Inventor： BOULET JEAN-YVES , TANNHOF PASCAL , PAILLET GUY
Abstract: In a neural network comprised of a plurality of N neuron circuits, each having calculated the distance (D1, ... , D4) coded on p bits (D1 = d11 ... d41) between an input vector and the prototype vector stored in the weight memory thereof, there is disclosed an aggregate circuit (517) comprised of N search/sort circuits (502-1, ..., 502-4) each being placed in a neuron circuit. The search/sort circuit is adapted to determine the minimum distance among said calculated distances. Each search/sort circuit (502-1) is comprised of p elementary base units (510-11 to 510-41) connected in series and disposed in a column direction. The distance bit signals of the same bit rank are applied to said base units according a line direction. As a consequence, the base units of the aggregate circuit are organized in a matrix. The feedback signal corresponds to the signal obtained by performing an OR function in an OR gate (12.1) between all the local output signals generated by the base units of a determined line. The search process is based on the search of zeroes in the distance bit signals, from the MSB's to the LSB's. If a zero is found in a determined line, all the columns which have a one in this line are excluded from the following search. The process is continued until it remains only one distance: the searched minimum distance, that is finally available at the output of the said OR circuit. The above described search/sort circuit can be significantly improved by adjoining a latch based circuit so that the aggregate circuit is now capable to sort the remaining distances in an increasing order.
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公开(公告)号：DE69430870D1
公开(公告)日：2002-08-01
申请号：DE69430870
申请日：1994-07-28
Applicant: IBM , PAILLET GUY
Inventor： BOULET JEAN YVES , GODEFROY CATHERINE , STEIMLE ANDRE , LOUIS DIDIER , PAILLET GUY , TANNHOF PASCAL
Abstract: In a neural network comprised of a plurality of neuron circuits, there is disclosed an improved neuron circuit architecture (11) that generates local result signals, e.g. of the fire (F) type and a local output signal of the distance or category type. The neuron circuit which is connected to buses which transport input data (e.g. the input category) and control signals includes the following circuits. A multi-norm distance evaluation circuit (300) calculates the distance D between the input vector (A) and the prototype vector (B) stored in a R/W (weight) memory circuit (250). A distance compare circuit (300) compares the distance D with either the actual influence field (AIF) of the stored prototype vector or the lower limit thereof (MinIF) to generate first and second intermediate signals (LT, LTE). An identification circuit (400) processes the said intermediate result signals, the input category signal (CAT), the local category signal (C) and a feedback signal (OR) to generate the local result signals which represent the response of a neuron circuit to the presentation of an input vector. A minimum distance determination circuit (500) is adapted to determine the minimum distance Dmin among all the distances calculated by all the neuron circuits of the neural network to generate a local output signal (NOUT) of the distance type. The same processing applies to categories. The feed-back signal which is collectively generated by all the neuron circuits results of ORing all the local distances/categories. A daisy chain circuit (600) is serially connected to the corresponding daisy chain circuits of the two adjacent neuron circuits to structure the neural network as a chain. Its role is to determine the neuron circuit state: free (in particular, the first free in the chain) and engaged. Finally, a context circuitry (100/150) is capable to allow or not the neuron circuit to participate with the other neuron circuits in the generation of the said feed-back signal.
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