公开(公告)号：DE69527761D1

公开(公告)日：2002-09-19

申请号：DE69527761

申请日：1995-11-02

Applicant: SIEMENS AG ,  IBM

Inventor： CONRU HAROLD WARD ,  FROEBEL FRANCIS EUGENE ,  GREGORITSCH JR ,  RIELEY SHELDON COLE ,  STARR STEPHEN GEORGE ,  UTTRECHT RONALD ROBERT ,  WHITE ERIC JEFFREY ,  POHL JENS GUENTER

IPC: H01L23/50 ,  H01L23/00 ,  H01L23/495

Abstract: A lead on chip (LOC) semiconductor leadframe package provides notched lead-fingers (60) to eliminate mechanical shear-stress at the peripheral edge of a semiconductor chip (52). Opposite rows of substantially flat cantilevered lead-fingers (60) are attached by double-sided adhesive tape (55) in thermal contact with the active face of a chip (52). The lead-fingers (60) are routed in personalized paths over the face of the chip (52) to cover a large surface area to aid heat dissipation. All wirebond connections (63) between the lead-fingers (60) and the chip (52) are made at a centerline connection strip running down the center of the chip (52). Each of the cantilevered lead-fingers (60) has a notched portion positioned directly over the vulnerable peripheral chip edge to reduce thermal, mechanical shear-stress. Additionally, since corrosion typically follows a lead path, the notch provides an increasing path length to prevent corrosive ingress over the chip face.

公开(公告)号：DE69527761T2

公开(公告)日：2003-04-03

申请号：DE69527761

申请日：1995-11-02

Applicant: SIEMENS AG ,  IBM

Inventor： CONRU HAROLD WARD ,  FROEBEL FRANCIS EUGENE ,  GREGORITSCH JR ,  RIELEY SHELDON COLE ,  STARR STEPHEN GEORGE ,  UTTRECHT RONALD ROBERT ,  WHITE ERIC JEFFREY ,  POHL JENS GUENTER

IPC: H01L23/50 ,  H01L23/00 ,  H01L23/495

Abstract: A lead on chip (LOC) semiconductor leadframe package provides notched lead-fingers (60) to eliminate mechanical shear-stress at the peripheral edge of a semiconductor chip (52). Opposite rows of substantially flat cantilevered lead-fingers (60) are attached by double-sided adhesive tape (55) in thermal contact with the active face of a chip (52). The lead-fingers (60) are routed in personalized paths over the face of the chip (52) to cover a large surface area to aid heat dissipation. All wirebond connections (63) between the lead-fingers (60) and the chip (52) are made at a centerline connection strip running down the center of the chip (52). Each of the cantilevered lead-fingers (60) has a notched portion positioned directly over the vulnerable peripheral chip edge to reduce thermal, mechanical shear-stress. Additionally, since corrosion typically follows a lead path, the notch provides an increasing path length to prevent corrosive ingress over the chip face.

公开(公告)号：AT222402T

公开(公告)日：2002-08-15

申请号：AT95480162

申请日：1995-11-02

Applicant: IBM ,  SIEMENS AG

Inventor： CONRU HAROLD WARD ,  FROEBEL FRANCIS EUGENE ,  GREGORITSCH ALBERT JOHN JR ,  RIELEY SHELDON COLE ,  STARR STEPHEN GEORGE ,  UTTRECHT RONALD ROBERT ,  WHITE ERIC JEFFREY ,  POHL JENS GUENTER

IPC: H01L23/50 ,  H01L23/00 ,  H01L23/495

Abstract: A lead on chip (LOC) semiconductor leadframe package provides notched lead-fingers (60) to eliminate mechanical shear-stress at the peripheral edge of a semiconductor chip (52). Opposite rows of substantially flat cantilevered lead-fingers (60) are attached by double-sided adhesive tape (55) in thermal contact with the active face of a chip (52). The lead-fingers (60) are routed in personalized paths over the face of the chip (52) to cover a large surface area to aid heat dissipation. All wirebond connections (63) between the lead-fingers (60) and the chip (52) are made at a centerline connection strip running down the center of the chip (52). Each of the cantilevered lead-fingers (60) has a notched portion positioned directly over the vulnerable peripheral chip edge to reduce thermal, mechanical shear-stress. Additionally, since corrosion typically follows a lead path, the notch provides an increasing path length to prevent corrosive ingress over the chip face.

公开(公告)号：DE69229489D1

公开(公告)日：1999-08-05

申请号：DE69229489

申请日：1992-04-07

Applicant: IBM

Inventor： CONRU WARD H ,  IRISH GARY HUGH ,  PAKULSKI FRANCIS JOSEPH ,  SLATTERY WILLIAM JOHN ,  STARR STEPHEN GEORGE ,  WARD WILLIAM CAROLL

IPC: H01L21/60 ,  H01L21/56 ,  H01L23/495 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18 ,  H01L21/50 ,  H01L23/24

Abstract: This is a semiconductor chip (12) in which the conductive path between the chip and the lead frame (14) via wires (16) can be easily and reproduceably improved. This is accomplished by improving the bond between the wires and the lead frame members to which the wires are joined and by creating additional contacts between each wire and its respective lead even if the bonded contact breaks or fails at or immediately adjacent to the bonding point. This is accomplished by placing an insulating layer (11b) on the active surface of each chip, carrying input and output bonding pads thereon, to which lead frame conductors have been connected by bonding wires. The insulating layer is a thermosetting adhesive (17) and is placed over the lead frame, the bonding wires and the active face of the semiconductor chip so that when a lamination force is applied to the insulating layer the wires will be crushed and held against their respective pads and against the respective leads to which they are connected and the active face of the semiconductor protected by the adhesive bonding thereto. In this way greater contact between the wires and the leads is enhanced and defects or failure in conductivity therebetween reduced or eliminated.

公开(公告)号：DE69229489T2

公开(公告)日：2000-01-20

申请号：DE69229489

申请日：1992-04-07

Applicant: IBM

Inventor： CONRU WARD H ,  IRISH GARY HUGH ,  PAKULSKI FRANCIS JOSEPH ,  SLATTERY WILLIAM JOHN ,  STARR STEPHEN GEORGE ,  WARD WILLIAM CAROLL

IPC: H01L21/60 ,  H01L21/56 ,  H01L23/495 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18 ,  H01L21/50 ,  H01L23/24

Abstract: This is a semiconductor chip (12) in which the conductive path between the chip and the lead frame (14) via wires (16) can be easily and reproduceably improved. This is accomplished by improving the bond between the wires and the lead frame members to which the wires are joined and by creating additional contacts between each wire and its respective lead even if the bonded contact breaks or fails at or immediately adjacent to the bonding point. This is accomplished by placing an insulating layer (11b) on the active surface of each chip, carrying input and output bonding pads thereon, to which lead frame conductors have been connected by bonding wires. The insulating layer is a thermosetting adhesive (17) and is placed over the lead frame, the bonding wires and the active face of the semiconductor chip so that when a lamination force is applied to the insulating layer the wires will be crushed and held against their respective pads and against the respective leads to which they are connected and the active face of the semiconductor protected by the adhesive bonding thereto. In this way greater contact between the wires and the leads is enhanced and defects or failure in conductivity therebetween reduced or eliminated.