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    METALLIZATION STRUCTURE
    1.
    发明专利
    METALLIZATION STRUCTURE 失效

    公开(公告)号：JPH10308362A

    公开(公告)日：1998-11-17

    申请号：JP11245598

    申请日：1998-04-22

    Applicant: IBM ,  TOSHIBA CORP

    Inventor： USUI TAKAMASA ,  DEHAVEN PATRICK W ,  RODBELL KENNETH P ,  FILIPPI RONALD G

    IPC: C23C14/14 ,  C23C16/06 ,  C23C28/02 ,  H01L21/28 ,  H01L21/285

    Abstract: PROBLEM TO BE SOLVED: To provide a metallization structure, which is small in resistivity, has excellent electricity transfer characteristics and at the same time, is textured to a high degree, and moreover, to prevent the formation of a hillock on the structure by a method wherein aluminium layers, aluminium alloy layers or both layers of the aluminium layers and the aluminum alloy layers, which come into contact electrically with tower group IVA metal layers having a thickness in a specified range, are formed. SOLUTION: Four or five-layer interconnected metallized layers are formed on interlayer stud connection layers 10, which are encircled with an insulator 8 and are connected with a silicon substratelike device substrate 6. Lower group IVA metal layers 13 consist of a titanium layer and the thickness of a metallization structure is about 90 to about 110 angstroms. By limiting this thickness, the structure of a metal layer, which is added afterwards, and the texture of the metal layer are controlled. Layers 15 to come into contact electrically with the lower layers 13 are aluminium layers or aluminium alloy layers. Titanium nitride layers 14 on the lower layers 13 prevent a reaction of the aluminium layers 15 with the lower layers 13 and capping layers consisting of titanium layers 18 and titanium nitride layers 19 perform an antireflection action.

    Semiconductor device and manufacturing method thereof
    3.
    发明专利
    Semiconductor device and manufacturing method thereof 有权
    半导体器件及其制造方法

    公开(公告)号：JP2008091830A

    公开(公告)日：2008-04-17

    申请号：JP2006273948

    申请日：2006-10-05

    Applicant: Toshiba Corp ,  株式会社東芝

    Inventor： WADA MAKOTO ,  OUCHI KAZUYA ,  USUI TAKAMASA

    IPC: H01L21/768 ,  H01L21/28 ,  H01L21/3205 ,  H01L23/52

    CPC classification number: H01L23/485 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76858 ,  H01L21/76864 ,  H01L21/76867 ,  H01L21/76873 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device, along with its manufacturing method, that has a wiring structure of high reliability and low electric resistance. SOLUTION: The semiconductor device comprises a semiconductor substrate, a silicide layer formed on the semiconductor substrate, an interlayer insulating film formed on the silicide layer, a metal layer which is formed in the interlayer insulating film and is electrically connected to the silicide layer by way of a contact film, and a diffusion barrier film which is formed between the metal layer and the interlayer insulating film. The contact film comprises metal element contained in the metal layer, metal element contained in the diffusion barrier film, and metal element contained in the silicide layer or Si, by at least one, respectively. COPYRIGHT: (C)2008,JPO&INPIT

    Abstract translation: 要解决的问题：提供具有高可靠性和低电阻的布线结构的半导体器件及其制造方法。 解决方案：半导体器件包括半导体衬底，形成在半导体衬底上的硅化物层，形成在硅化物层上的层间绝缘膜，形成在层间绝缘膜中并与硅化物电连接的金属层 层，以及形成在金属层和层间绝缘膜之间的扩散阻挡膜。 接触膜包括分别包含在金属层中的金属元素，包含在扩散阻挡膜中的金属元素和包含在硅化物层或Si中的金属元素。 版权所有（C）2008，JPO＆INPIT

    Micro electro-mechanical system and its manufacturing method
    5.
    发明专利
    Micro electro-mechanical system and its manufacturing method 审中-公开
    微电子机械系统及其制造方法

    公开(公告)号：JP2008137139A

    公开(公告)日：2008-06-19

    申请号：JP2006328140

    申请日：2006-12-05

    Applicant: Toshiba Corp ,  Toshiba Microelectronics Corp ,  東芝マイクロエレクトロニクス株式会社 ,  株式会社東芝

    Inventor： OGURO TATSUYA ,  IKEHASHI TAMIO ,  USUI TAKAMASA ,  HAYASHI HIROMI ,  TSUMURA KAZUMICHI ,  NASU ISATO

    IPC: B81B3/00 ,  B81C1/00 ,  H01L23/02

    CPC classification number: H01L2224/48091 ,  H01L2924/00014

    Abstract: PROBLEM TO BE SOLVED: To provide a reliable micro electro-mechanical system and its manufacturing method. SOLUTION: The micro electro-mechanical system comprises a micro electro-mechanical structural body 3 formed on a substrate 2, a frame member 4 formed on the substrate 2 so as to surround the micro electro-mechanical structural body 3, a hollow film 6 which covers the frame member 4 and forms a cavity 5 between the film 6 and micro electro-mechanical structural body 3, and a sealing layer 7 which is laminated on the hollow film 6 and seals the micro electro-mechanical structural body 3 in the cavity 5. COPYRIGHT: (C)2008,JPO&INPIT

    Abstract translation: 要解决的问题：提供可靠的微机电系统及其制造方法。 解决方案：微电子机械系统包括形成在基板2上的微电子机械结构体3，形成在基板2上以围绕微电子机械结构体3的框架部件4，中空 膜6，其覆盖框架构件4并在膜6和微机电结构体3之间形成空腔5，以及层压在中空膜6上并将微电子机械结构体3密封的密封层7 空腔5.版权所有（C）2008，JPO＆INPIT

    Semiconductor device and method for manufacturing same
    6.
    发明专利
    Semiconductor device and method for manufacturing same 有权
    半导体器件及其制造方法

    公开(公告)号：JP2007073905A

    公开(公告)日：2007-03-22

    申请号：JP2005262502

    申请日：2005-09-09

    Applicant: Toshiba Corp ,  Toshiba Microelectronics Corp ,  東芝マイクロエレクトロニクス株式会社 ,  株式会社東芝

    Inventor： HAYASHI HIROMI ,  NASU ISATO ,  TSUMURA KAZUMICHI ,  USUI TAKAMASA ,  TANIMOTO KOKICHI

    IPC: H01L21/8242 ,  H01L21/316 ,  H01L27/108

    CPC classification number: H01L29/945 ,  H01L27/10852 ,  H01L27/1087 ,  H01L28/40 ,  H01L29/66181

    Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device having a capacitor insulating film with high performance whose film thinning and making uniform is achievable with a high dielectric constant. SOLUTION: Transistors 13 and 14 formed on a semiconductor substrate are provided with a gate electrode formed through a gate insulating film, and first and second diffusion layers formed in the semiconductor substrate positioned at the both sides of the gate electrode. The first electrodes 15 and 16 are connected to the first diffusion layer of the transistor. A capacitor insulating film 17 formed on the first electrode is formed by a silicon oxide film containing substances whose diffusion speed is faster than that of Cu, and which is easier to react to oxygen than Cu. A second electrode formed on the capacitor insulating film is formed of one of a Cu layer and a Cu layer containing the substances. COPYRIGHT: (C)2007,JPO&INPIT

    Abstract translation: 要解决的问题：为了提供一种具有高性能的电容器绝缘膜的半导体器件，其薄膜变薄和均匀可实现高介电常数。 形成在半导体衬底上的晶体管13和14设置有通过栅极绝缘膜形成的栅电极，以及形成在位于栅电极两侧的半导体衬底中的第一和第二扩散层。 第一电极15和16连接到晶体管的第一扩散层。 形成在第一电极上的电容绝缘膜17由含有扩散速度比Cu快的物质的氧化硅膜形成，并且比Cu更容易与氧反应。 形成在电容器绝缘膜上的第二电极由包含这些物质的Cu层和Cu层中的一个形成。 版权所有（C）2007，JPO＆INPIT

    半導体装置
    8.
    发明专利
    半導体装置 审中-公开
    半导体器件

    公开(公告)号：JP2015060918A

    公开(公告)日：2015-03-30

    申请号：JP2013192994

    申请日：2013-09-18

    Applicant: 株式会社東芝 ,  Toshiba Corp

    Inventor： KANEKO HAJIME ,  SHIMADA KEIICHI ,  USUI TAKAMASA

    IPC: H01L21/8247 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

    CPC classification number: H01L27/0207 ,  H01L21/764 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/5226 ,  H01L27/11519 ,  H01L27/11531 ,  H01L27/11565 ,  H01L27/11573 ,  H01L2924/0002 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/00

    Abstract: 【課題】コンタクトプラグと隣接するビット線との間に発生するリーク電流を抑制する半導体装置を提供する。【解決手段】半導体装置は、半導体基板1と、上端部の径寸法が下端部の径寸法よりも大きい第1コンタクトプラグ6と、第1コンタクトプラグ6を覆う第1絶縁膜4と、下端部が第1コンタクトプラグ6の上端部に接合され、上端部の径寸法が下端部の径寸法よりも小さい第2コンタクトプラグ9と、第2コンタクトプラグ9を覆う第2絶縁膜7と、下端部に第2コンタクトプラグ9の上端部が接合された配線層13と、配線層13を覆う第3絶縁膜10、11と、第1コンタクトプラグ6の上端部のうちの第2コンタクトプラグ9の下端部で覆われない部分に形成された段差6aを備えた。【選択図】図1

    Abstract translation: 要解决的问题：提供抑制接触塞和相邻位线之间发生的漏电流的半导体器件。解决方案：半导体器件包括：半导体衬底1; 第一接触插塞6，其直径尺寸在上端大于下端的直径尺寸; 覆盖第一接触插塞6的第一绝缘膜4; 第二接触插塞9，其下端连接到第一接触插塞6的上端，并且其上端的直径尺寸小于下端的直径尺寸; 覆盖第二接触插塞9的第二绝缘膜7; 布线层13，其下端与第二接触插塞9的上端接合; 覆盖布线层13的第三绝缘膜10,11; 以及形成在第一接触插头6的上端的一部分处的台阶部6a，其中第二接触插塞9的下端不覆盖。

    Method for manufacturing semiconductor substrate, and method for manufacturing semiconductor device
    9.
    发明专利
    Method for manufacturing semiconductor substrate, and method for manufacturing semiconductor device 审中-公开
    制造半导体基板的方法和制造半导体器件的方法

    公开(公告)号：JP2010034323A

    公开(公告)日：2010-02-12

    申请号：JP2008195381

    申请日：2008-07-29

    Applicant: Toshiba Corp ,  株式会社東芝

    Inventor： USUI TAKAMASA ,  WATABE TADAYOSHI ,  TOMIZAWA HIDEYUKI

    IPC: H01L21/3205 ,  H01L21/28 ,  H01L21/336 ,  H01L21/76 ,  H01L23/52 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78

    Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor substrate and a method for manufacturing a semiconductor device capable of preventing ingress and diffusion of metal elements, causing performance degradation, into a semiconductor substrate. SOLUTION: The method for manufacturing the semiconductor substrate includes a process of forming a nitride film 2 on both sides and a side surface of a semiconductor substrate 1, a process of laminating an oxide film 3 containing a silicon and a precursor film 4A containing a predetermined metal all over the surface of the nitride film 2, and a process of forming a self-forming barrier film 4 containing the silicon and the predetermined metal in a self-alignment manner by making the oxide film 3 react with the precursor film 4A. COPYRIGHT: (C)2010,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种半导体衬底的制造方法以及能够防止金属元素的进入和扩散，导致性能劣化的半导体器件的制造方法。 解决方案：制造半导体衬底的方法包括在半导体衬底1的两侧和侧面上形成氮化物膜2的工艺，层叠含有硅的氧化物膜3和前体膜4A的工艺 在氮化膜2的整个表面上含有预定的金属，以及通过使氧化膜3与前体膜反应而以自对准的方式形成含有硅和预定金属的自形成阻挡膜4的工艺 4A。 版权所有（C）2010，JPO＆INPIT

    Semiconductor device and method of manufacturing semiconductor device
    10.
    发明专利
    Semiconductor device and method of manufacturing semiconductor device 审中-公开
    半导体器件及制造半导体器件的方法

    公开(公告)号：JP2009278000A

    公开(公告)日：2009-11-26

    申请号：JP2008129819

    申请日：2008-05-16

    Applicant: Toshiba Corp ,  株式会社東芝

    Inventor： HAYASHI HIROMI ,  MATSUNAGA NORIAKI ,  USUI TAKAMASA

    IPC: H01L21/3205 ,  H01L23/52

    CPC classification number: H01L21/76846 ,  H01L21/76847 ,  H01L21/76849 ,  H01L21/76867 ,  H01L21/76877 ,  H01L21/76886 ,  H01L21/76888 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device that prevents excessive Si of a compound film and containing Cu and Si formed on Cu wiring from being diffused into the Cu wiring. SOLUTION: The semiconductor device includes Cu films 260 and 262 forming the Cu wiring having a region where Si and O are contained more than others, a selective cap film 280 formed selectively on the Cu films 260 and 262 and containing Cu and Si, and an interlayer insulating film 220 formed on side face sides of the Cu films 260 and 262. COPYRIGHT: (C)2010,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种半导体器件，其防止在Cu布线上形成的包含Cu和Si的化合物膜的过量Si扩散到Cu布线中。 解决方案：半导体器件包括形成Cu布线的Cu膜260和262，其具有比其它Si和O多的区域，选择性盖膜280选择性地在Cu膜260和262上形成并且包含Cu和Si ，以及形成在Cu膜260和262的侧面侧的层间绝缘膜220.权利要求：（C）2010，JPO＆INPIT

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