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公开(公告)号：CA2166369A1
公开(公告)日：1997-06-30
申请号：CA2166369
申请日：1995-12-29
Applicant: IBM CANADA
Inventor： BLAINEY ROBERT JAMES
IPC: G06F9/45
Abstract: A system and method for determining alias information at the intercompilation unit level of a compilation process includes the steps of determining antialias sets from the alias information provided by the first stage of the compilation process, calculating pessimistic inter-compilation unit alias sets and refining these sets, after transitive closure as appropriate, with the anti-alias sets.
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公开(公告)号：CA2288614A1
公开(公告)日：2001-05-08
申请号：CA2288614
申请日：1999-11-08
Applicant: IBM CANADA
Inventor： BLAINEY ROBERT JAMES , ARCHAMBAULT ROCH GEORGES
IPC: G06F9/45
Abstract: Loop allocation for optimizing compilers includes the generation of a progra m dependence graph for a source code segment. Control dependence graph representations of the nested loops, from innermost to outermost, are generated and data dependence graph representations are generated for each level of nested loop as constrained by the control dependence graph. An interference graph is generated with the nodes of the data dependence graph. Weights are generated for the edges of the interference graph reflecting the affinity between statements represented by the nodes joined by the edges. Nodes in the interference graph are given weights reflecting resource usage by the statements associated with the nodes. The interference graph is partitioned using a profitability test based on the weights of edges and nodes and on a correctness test based on the reachability of nodes in the data dependence graph. Code is emitted based on the partitioned interference graph.
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Patent Agency Ranking
公开(公告)号：CA2166253A1
公开(公告)日：1997-06-29
申请号：CA2166253
申请日：1995-12-28
Applicant: IBM CANADA
IPC: G06F9/45
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公开(公告)号：CA2166252A1
公开(公告)日：1997-06-29
申请号：CA2166252
申请日：1995-12-28
Applicant: IBM CANADA
IPC: G06F9/45
Abstract: An interprocedural compilation method for aggregating global data variables in external storage to maximize data locality. Using the information displayed in a weighted interference graph in which node weights represent the size of data stored in each global variable and edges between variables represent access relationships between the globals, the global variables can be mapped into aggregates based on this frequency of access, while preventing the cumulative data size in any aggregate from exceeding a memory size restriction.
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公开(公告)号：CA2288614C
公开(公告)日：2004-05-11
申请号：CA2288614
申请日：1999-11-08
Applicant: IBM CANADA
Inventor： BLAINEY ROBERT JAMES , ARCHAMBAULT ROCH GEORGES
IPC: G06F9/45
Abstract: Loop allocation for optimizing compilers includes the generation of a progra m dependence graph for a source code segment. Control dependence graph representations of the nested loops, from innermost to outermost, are generated and data dependence graph representations are generated for each level of nested loop as constrained by the control dependence graph. An interference graph is generated with the nodes of the data dependence graph. Weights are generated for the edges of the interference graph reflecting the affinity between statements represented by the nodes joined by the edges. Nodes in the interference graph are given weights reflecting resource usage by the statements associated with the nodes. The interference graph is partitioned using a profitability test based on the weights of edges and nodes and on a correctness test based on the reachability of nodes in the data dependence graph. Code is emitted based on the partitioned interference graph.
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公开(公告)号：CA2166254A1
公开(公告)日：1997-06-29
申请号：CA2166254
申请日：1995-12-28
Applicant: IBM CANADA
IPC: G06F9/45
Abstract: A technique used during interprocedural compilation in which program objects are grouped together based on the weights of the connections between the objects and their costs. System-imposed constraints on memory size can be taken into account to avoid creating groupings that overload the system's capacity. The groupings can be distributed over memories located on different processors.
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公开(公告)号：CA2365375A1
公开(公告)日：2003-06-18
申请号：CA2365375
申请日：2001-12-18
Applicant: IBM CANADA
Inventor： HALL CHARLES BRIAN , ZHANG YINGWEI , BLAINEY ROBERT JAMES , ARCHAMBAULT ROCH GEORGES
Abstract: An embodiment of the present invention provides an optimizer for optimizing source code to generate optimized source code having instructions for instructing a central processing unit (CPU) to iteratively compute values for a primary recurrence element. A computer programmed loop for computing the primary recurrence element and subsequent recurrence elements is an example of a case involving iteratively computing the primary recurrence element. The CPU is operatively coupled to fast operating memory (FOM) and operativel y coupled to slow operating memory (SOM). SOM stores the generated optimized source code. The optimized source code includes instructions for instructing said CPU to stor e a computed value of the primary recurrence element in a storage location of FOM. The instructions also includes instructions to consign the computed value of the primary recurrence element from the storage location to another storage location of the FOM.
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