公开(公告)号：CA2369621C

公开(公告)日：2009-06-09

申请号：CA2369621

申请日：2002-01-25

Applicant: IBM CANADA

Inventor： WINER MICHAEL J ,  ZHENG ROGER L Q ,  HURAS MATTHEW A ,  GOSS JEFFREY J ,  FLASZA MIROSLAW A ,  POSNER SARAH ,  MEADOWCROFT LORYSA M ,  MCARTHUR CATHERINE S

IPC: G06F9/50 ,  G06F9/46 ,  G06F12/00 ,  G06F12/14 ,  G06F13/14 ,  G06F17/30

Abstract: The present invention is directed at a method and apparatus for handling resource transaction requests. By marking a waiting transaction request, having an access mode which is incompatible with the access mode of at least one of the executing transactions, with an ignore bit, a subsequent transaction request with an access mode compatible with the access mode(s) o f the executing transaction(s) may receive access to the resource. The subsequent transactio n request is then marked with a bypass indicator such that when the executing transactions are finish ed accessing the resource, the waiting transaction request may be notified it may have access to the resource. By including the ignore bit, each subsequent transaction request which arrives after ignore b it has been set, does not suffer from starvation.

公开(公告)号：CA2369621A1

公开(公告)日：2003-07-25

申请号：CA2369621

申请日：2002-01-25

Applicant: IBM CANADA

Inventor： POSNER SARAH ,  FLASZA MIROSLAW A ,  WINER MICHAEL J ,  ZHENG ROGER L Q ,  HURAS MATTHEW A ,  GOSS JEFFREY J ,  MEADOWCROFT LORYSA M ,  MCARTHUR CATHERINE S

IPC: G06F9/46 ,  G06F12/00 ,  G06F12/14 ,  G06F13/14 ,  G06F17/30

Abstract: The present invention is directed at a method and apparatus for handling resource transaction requests. By marking a waiting transaction request, having an access mode which is incompatible with the access mode of at least one of the executing transactions, with an ignore bit, a subsequent transaction request with an access mode compatible with the access mode(s) of the executing transaction(s) may receive access to the resource. The subsequent transaction request is then marked with a bypass indicator such that when the executing transactions are finished accessing the resource, the waiting transaction request may be notified it may have access to the resource. By including the ignore bit, each subsequent transaction request which arrives after ignore bit has been set, does not suffer from starvation.

公开(公告)号：CA2426606A1

公开(公告)日：2004-10-25

申请号：CA2426606

申请日：2003-04-25

Applicant: IBM CANADA

Inventor： MCARTHUR CATHERINE S ,  HURAS MATTHEW A ,  THORNBOROUGH SHAUN K ,  WINER MICHAEL J ,  HONG QUANHUA CLAIRE ,  ZHENG ROGER L Q ,  MEADOWCROFT LORYSA M

IPC: G06F16/901 ,  G06F17/30 ,  G06F12/02 ,  G06F17/40

Abstract: The present invention is directed to using a memory buffer to facilitate log catchup for online operations. Some designated areas of memory are allocated for one or more buffers for use during online operations (e.g. reorganization, create index, etc.). Concurrent update activities to the target object write informational records into the one or more buffer s. If the buffers become full, the informational records may be written to logs for persistent storage. After online operations finish building all or a suitable portion of the shadow object, l og catchup is performed by first applying activities in the informational records from the buffer an d thereafter applying activities from logs, if necessary. The invention helps solve the drawbacks of log catchup since the buffer contains only the information related to the target shadow object . Also it does not involve physical I/Os, as these records are all in memory.